Undoped Polysilicon Research Articles

Analysis of anomalous C-V behavior for extracting the traps density in the undoped polysilicon with a double-BOX structure

A new Double-BOX structure is introduced to reveal the electrical properties of undoped polysilicon used to enhance the performance of radio frequency SOI substrates. A plateau is clearly observed in the capacitance–voltage (C-V) characteristics, which is due to the influence of the potential barrier formed at the grain boundary. A tangential approximation method based on a three-element circuit model is proposed for correcting the measured C-V curve. With the corrected C-V curve, the effective trap density distribution in polysilicon is determined for each frequency.

Si/Si0.7Ge0.3 A2RAM nanowires fabrication and characterization for 1T-DRAM applications

A2RAM devices are fabricated using an adaptation of Si-nanowire process flow, including a Si-SiGe heterostructure. We present the effects of gate length, film thickness, bridge implantation conditions and the presence of LDD impacts on A2RAM memory performance. Despite the accidentally undoped polysilicon gate, we succeed in demonstrating 1T-DRAM programming and operation.

Growth and Characterization of Undoped Polysilicon Thick Layers: Revisiting an Old System

Thick layer of polycrystalline silicon (poly-Si) grown by Atmospheric Pressure Chemical Vapor Deposition (APCVD) is still a reference material in a number of applications, despite the high thermal budget of this technique. This work presents a material study of undoped poly-Si layers of different thicknesses, using different characterization techniques such as secondary electron microscope in backscattered detection configuration, electron backscattering diffraction imaging, secondary ion mass spectrometry and spreading resistance profiling. The poly-Si layers, grown at 1000 °C by APCVD on thermal oxide, were found to have a columnar microstructure with [110] main orientation. By correlating layer purity, grain size and electrical resistivity, no straightforward relation between grain size and resistivity could be found. The layers resistivity is found almost independent on thickness and thus grain size. The possible reasons for such difference with previous other works are discussed taking into account the grain size determination uncertainty and the electrical characterization limitations.

Influence of Polysilicon Deposition Conditions on Advanced 3D NAND

As the conductive channel, undoped channel hole polysilicon (poly-Si) plays a significant role in 3D NAND. Two important properties i.e. grain size and step coverage (S/C) of undoped channel hole poly-Si have attracted great attentions in practical manufacturing. The grain size affects the mobility of conductive poly-Si film and large grain size usually leads to high mobility. The step coverage influences the subthreshold swing (SS) and improved step coverage leads to small SS. In this paper, during the growth of poly-Si, the influence of different deposition conditions, such as temperature and gas source ratio between Si2H6 and SiH4, on the grain size and step coverage is investigated comprehensively. Grain size and step coverage are characterized using by Transmission Electron Microscope (TEM) and Precession Electron Diffraction (PED). It is found that as the decrease of deposition temperature, both the grain size and step coverage are improved. Compared to gas source SiH4, the employment of Si2H6 is beneficial in achieving large grain size to some degree and no further improvement can be obtained when the flow of Si2H6 is increased to a certain value. However, as-deposited poly-Si exhibits poorer step coverage using Si2H6 in contrast to SiH4.

Charge Accumulation in MOS Structures with a Polysilicon Gate under Tunnel Injection

Charge accumulation in metal—oxide—semiconductor (MOS) structures with a doped and undoped polysilicon gate with Al contacts and without them under tunnel electron injection from the gate and silicon substrate is investigated. It is shown that negative charge is accumulated near the polysilicon gate irrespective of the injection polarity, and positive charge is accumulated near the silicon substrate. Negative charge also appears near the silicon substrate at large injection charges. The results are described with the help of a numerical model, in which the formation of electron traps with the deposition of Al contacts and the generation of electron traps during the recombination of free electrons with holes captured at traps is taken into account.

A high-speed lateral PIN polysilicon photodiode on standard bulk CMOS process

This paper reports a lateral PIN polysilicon photodiode on standard bulk complementary metal-oxidesemiconductor (CMOS) process for monolithically integrated high-speed optoelectronic integrated circuits (OEIC). A nominal undoped polysilicon as the photodetection area is intentionally created without introducing any process modification. With the device area of 50×50μm2, a measured responsivity of 46mA/W and a quantum efficiency of 11% were observed under the reverse voltage of 10V and the wavelength of 520nm. A compact equivalent circuit model for the proposed lateral photodiode is built to analyze the frequency response, and a bandwidth of over 20GHz was obtained from the measured data, which is to the best of our knowledge the largest bandwidth ever reported based on standard bulk CMOS process.

Influence of Deuterium Treatments on the Polysilicon-Based Metal-Semiconductor-Metal Photodetector.

The electrical behavior of metal-semiconductor-metal (MSM) Schottky barrier photodetector structure, depending on deuterium treatment, is analyzed by means of the dark current and the photocurrent measurements. Al/Ti bilayer was used as Schottky metal. The deuterium incorporation into the absorption layer, undoped polysilicon, was achieved with annealing process and with ion implantation process, respectively. In the photocurrent-to-dark current ratio measurement, deuterium-ion-implanted photodetector shows over hundred higher than the control device. It means that the heightening of the Schottky barrier and the passivation of grain boundary trap were achieved effectively through the deuterium ion implantation process.

Improved Thermal Performance of SOI Using a Compound Buried Layer

The buried oxide (BOX) layer in silicon on insulator (SOI) was replaced by a compound buried layer (CBL) containing layers of ${\rm SiO}_{2}$ , polycrystalline silicon (polysilicon), and ${\rm SiO}_{2}$ . The undoped polysilicon in the CBL acted as a dielectric with a higher thermal conductivity than ${\rm SiO}_{2}$ . CBL provides a reduced thermal resistance with the same equivalent oxide thickness as a standard ${\rm SiO}_{2}$ buried layer. Thermal resistance was further reduced by lateral heat flow through the polysilicon. Reduction in thermal resistance by up to 68% was observed, dependent on polysilicon thickness. CBL SOI substrates were designed and manufactured to achieve a 40% reduction in thermal resistance compared with an 1.0- $\mu{\rm m}~{\rm SiO}_{2}$ BOX. Power bipolar transistors with an active silicon layer thickness of 13.5 $\mu{\rm m}$ manufactured on CBL SOI substrates showed a 5%–17% reduction in thermal resistance compared with the standard SOI. This reduction was dependent on transistor layout geometry. Between 65% and 90% of the heat flow from these power transistors is laterally through the thick active silicon layer. Analysis confirmed that CBL SOI provided a 40% reduction in the vertical path thermal resistance. Devices employing thinner active silicon layers will achieve the greater benefit from reduction in vertical path thermal resistance offered by CBL SOI.

Explicit solution of channel potential and drain current model in symmetric double-gate polysilicon TFTs

A physical and explicit surface potential model for undoped symmetric double-gate polysilicon thin-film transistors has been derived based on an effective charge density approach of Poisson's equation with both exponential deep and tail state terms included. The proposed surface potential calculation is single-piece and eliminates the regional approach. Model predictions are compared to numerical simulations with close agreement, having absolute error in the millivolt range. Furthermore, expressions of the drain current are given for a wide range of operation regions, which have been justified by thorough comparisons with experimental data.

P-type and N-type multi-gate polycrystalline silicon vertical thin film transistors based on low-temperature technology

P-type and N-type multi-gate vertical thin film transistors (vertical TFTs) have been fabricated, adopting the low-temperature (T⩽600°C) polycrystalline silicon (polysilicon) technology. Stacked heavily-doped polysilicon source and drain are electrically isolated by an insulating barrier. Multi-teeth configuration is defined by reactive ion etching leading to sidewalls formation on which undoped polysilicon active layer is deposited. All the polysilicon layers are deposited from low pressure chemical vapor deposition (LPCVD) technique. Vertical TFTs are designed with multi gates, in order to have a higher equivalent channel width. Different active layer thicknesses have been attempted, and an ION/IOFF ratio slightly higher than 105 is obtained. P-type and N-type vertical TFTs have shown symmetric electrical characteristics. Different geometrical parameters have been chosen. IOFF is proportional to the single channel width, and to the tooth number. ION is only proportional to the tooth number. These devices open the way of a CMOS-like technology.

Design of complementary LDMOS in 0.35 μm BiCMOS technology for smart integration

In this paper, an n LDMOS and a p LDMOS are developed by slight modifications of the base process steps of 0.35 μ m BiCMOS technology. Extra two masks are used for the formation of the body region and the drift region with slightly added thermal budget and without resorting to high-tilt implants. The specific ON-resistance (R ON, SP ) and the OFF-state breakdown voltage ( BV ) are 1.5 m Ω cm 2 and 60 V, for the n LDMOS and 3.0 m Ω cm 2 and 160 V, for the p LDMOS, so the devices can typically be operated around 42 V supply voltage, which is suitable for the new automotive applications. An isolation mechanism between the power devices is suggested using a deep trench filled with silicon dioxide and undoped polysilicon. The polysilicon has a nearly perfect conformal deposition, that is, both step coverage and bottom coverage are 100%. A simple subcircuit model is built using a two module approach, one for the intrinsic MOS area and the other for the drift region. The Spice model parameters of the intrinsic MOS part are extracted using a system that links the ICCAP extraction tool with the results of the ISE-TCAD tools. The simulation results using the Spice model are compared to the results provided by ISE-TCAD tools, and the accuracy at room temperature is less than 5% for the whole voltage domain. An interface circuit, to convert 0/3.3 V to 0/42 V, suitable for automotive applications, is proposed.

A continuous semi-empiric transfer characteristics model for surrounding gate undoped polysilicon nanowire MOSFETs

A new continuous semi-empiric compact model for the current transfer characteristics of surrounding gate undoped polycrystalline silicon (Poly-Si) nanowire (NW) MOSFETs is proposed. The model consists of a single equation based on the Lambert function, which contains only four parameters and is continuously valid and fully differentiable throughout weak and strong conduction regimes of operation. The model is tested on measured transfer characteristics of experimental devices. The extracted model parameters are used to generate transfer characteristics playbacks that are then compared to the measured data to validate the proposed model’s adequacy for these devices.

A Compact Model for Undoped Symmetric Double-Gate Polysilicon Thin-Film Transistors

A physics-based solution to the surface potential and potential in the middle of the film for the symmetric undoped or light-doped double-gate (DG) polysilicon thin-film transistors (poly-Si TFTs) has been derived from the one-dimensional (1-D) Poisson's equation. The calculation of the channel potential accounts for an exponential distribution of defect states' density. It provides a good description of surface potential over different regions of operation. Comparison with numerical data shows that the solution serves as a good approximation to potential under different conditions. The characteristics of the drain current at DG poly-Si TFTs based on terms of surface potential have been described and modeled in this paper. The resulting drain current characteristics show a good agreement with two-dimensional (2-D) numerical device simulations with a minimum of parameters, and also a good match to the DG poly-Si TFTs experimental data.

Role of amines and amino acids in enhancing the removal rates of undoped and P-doped polysilicon films during chemical mechanical polishing

During chemical mechanical polishing, removal rates of undoped and P-doped polysilicon films as high as 200 and 250 nm/min, respectively, have been achieved using several abrasive-free solutions, each consisting of an amine or amino acid. It was observed that only α-amine(s) solutions enhance the removal rates of both undoped and P-doped polysilicon films. Potentiodynamic, zeta potential, contact angle, thermo gravimetric and EDS measurements were performed to examine the role of these α-amines in achieving high polysilicon removal rate. Possible removal mechanism of both undoped and P-doped polysilicon film in the presence and absence of the different additives is also proposed.

Fabrication of polycrystalline silicon nanowires using conventional UV lithography

Silicon nanowires are processed by using the sidewall spacer formation technique. This technique uses craftily a drawback of anisotropic etching to go beyond optical limits with conventional UV lithography for precision patterns. The final width of the spacer is controlled by the steepness of the etching side and by the uniformity of the wall recovering layer. In our process, a polysilicon layer is deposited by low pressure chemical vapour deposition technique on SiO2 wall network patterned by conventional UV lithography technique. Accurate control of the etching rate of the polysilicon leads to the formation of nanometric size sidewall spacers with a curvature radius below 100nm. Networks of such parallel polysilicon nanowires were electrically tested in function of temperature (530K<T<200K). Results show that conductivity of undoped polysilicon nanowire is thermally activated at high temperature (T >300K) with thermal activation EA ∼ 0.3 eV

P형 in-situ 도핑 폴리실리콘 막질에 관한 연구

This paper reports physical properties of in situ boron doped silicon films made from boron source gas and silane (<TEX>$SiH_4$</TEX>) gas in a conventional low-pressure chemical vapor deposition vertical furnace. If the p-type polysilicon is formed by boron implantation into undoped polysilicon, the plasma nitridation (PN) process is added on the oxide in order to suppress boron penetration that can be caused during the thermal treatments used in fabrication. In-situ boron doped polysilicon deposition can complete p-type polysilicon film with only one deposition process and need not the PN process, because there is not interdiffusion of dopant at the intermediate temperatures of the subsequent steps. Since in-situ boron doped polysilicon films have higher work function than that of n-type polysilicon and they are compatible with the underlying oxide, they may be promising materials for improving memory cell characteristics if we make its profit of these physical properties.

A Highly Reliable Lateral MEMS Switch Utilizing Undoped Polysilicon as Isolation Material

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> The lateral actuated switch requires an isolation structure to provide mechanical coupling and electrical isolation between the actuator and the contacts. This isolation structure usually imposes extra difficulty on the fabrication process. In previous reports, we demonstrated a thermal actuated lateral switch, where the nitride isolation structure was a weak point, leading to reliability problems. In this paper, we developed a modified switch utilizing undoped polysilicon as the isolation material. The undoped-polysilicon isolation structure requires only one extra step of sheltered implantation, and it provides robust mechanical connection. A 20- <formula formulatype="inline"><tex>$\mu\hbox{m}$</tex></formula>-long undoped-polysilicon isolation structure has a current leakage of less than 2 nA under a 15-V operation voltage. The proposed switch works under a 12-V driving voltage with 60-mW input power. The time response is measured to be 130 <formula formulatype="inline"><tex>$\mu \hbox{s}$</tex></formula>, and a maximum operation frequency of 4.5 kHz is reached. An <emphasis emphasistype="smcaps">on</emphasis>-state insertion loss of <formula formulatype="inline"><tex>$-$</tex> </formula>0.41 dB at 20 GHz and an <emphasis emphasistype="smcaps">off</emphasis>-state isolation of <formula formulatype="inline"><tex>$-$</tex></formula>20 dB at 20 GHz have been achieved on the normal low-resistivity silicon substrate. The undoped-polysilicon isolation method can be used in other surface-micromachined lateral switches as well.<formula formulatype="inline"><tex>$\hfill$</tex></formula> [2007-0022] </para>

Effects of&amp;lt;tex&amp;gt;$hboxH_2$&amp;lt;/tex&amp;gt;Annealing and Polysilicon Emitter Structure on&amp;lt;tex&amp;gt;$hboxH_FE$&amp;lt;/tex&amp;gt;of n–p–n Bipolar Junction Transistors

This paper presents the effects of H/sub 2/ annealing and polysilicon emitter structures on H/sub FE/ characteristics of n-p-n bipolar junction transistors. The increase of the number of H/sub 2/ annealing steps results in the device performance (H/sub FE//spl times/V/sub A/) improvement by 27.8%, due to the formation of H-Si dangling bonds, which allow the decrease of the base current. In addition, the bilayer of undoped polysilicon deposition/ion implantation and in situ doped polysilicon in the ploy emitters greatly improve the level of H/sub FE/ reliability and 1/f noise characteristic. The experimental results of H-Si dangling bond property at the polysilicon grain boundaries and polysilicon interface with the H/sub 2/ annealing steps in n-p-n bipolar junction transistor formulation will be also presented.

Mechanical characterization of micro/nanoscale structures for MEMS/NEMS applications using nanoindentation techniques

Mechanical properties of micro/nanoscale structures are needed to design reliable micro/nanoelectromechanical systems (MEMS/NEMS). Micro/nanomechanical characterization of bulk materials of undoped single-crystal silicon and thin films of undoped polysilicon, SiO 2, SiC, Ni–P, and Au have been carried out. Hardness, elastic modulus and scratch resistance of these materials were measured by nanoindentation and microscratching using a nanoindenter. Fracture toughness was measured by indentation using a Vickers indenter. Bending tests were performed on the nanoscale silicon beams, microscale Ni–P and Au beams using a depth-sensing nanoindenter. It is found that the SiC film exhibits higher hardness, elastic modulus and scratch resistance as compared to other materials. In the bending tests, the nanoscale Si beams failed in a brittle manner with a flat fracture surface. The notched Ni–P beam showed linear deformation behavior followed by abrupt failure. The Au beam showed elastic–plastic deformation behavior. FEM simulation can well predict the stress distribution in the beams studied. The nanoindentation, scratch and bending tests used in this study can be satisfactorily used to evaluate the mechanical properties of micro/nanoscale structures for use in MEMS/NEMS.

Pulsed laser repair of adhered surface-micromachined polycrystalline silicon cantilevers

A technique for repairing adhered surface-micromachined polycrystalline silicon (polysilicon) structures using pulsed lasers has been developed, experimentally investigated, and modeled. Advantages of using lasers to repair adhered microfabricated structures include the ease of implementation, the ability to apply the laser energy locally to the adhered region, and the non-contact nature of the process. The amount of thermal heating is typically less than 100 °C and does not damage polysilicon structures. Pulsed laser repair has been successful for undoped and n-doped polysilicon microcantilevers that had adhered to the substrate during chemical etching of the sacrificial layers and subsequent drying. This paper reviews experiments investigating the use of Ti:sapphire and Nd:YAG laser systems to repair failed polysilicon microcantilevers. The first experiments used a Ti:sapphire laser system, and later experiments using a Nd:YAG laser produced repair yields up to 100% for 10 μm wide cantilevers that were as long as 1 mm with laser fluences of 70 mJ/cm2. While the Ti:sapphire laser experiments indicate contributions from both non-thermal and thermal mechanisms for the repair process, the Nd:YAG laser experimental results are consistent with a thermal mechanism, specifically thermal expansion. A thermomechanical model is presented which enables the prediction of the laser operating conditions needed for laser repair. The model calculates the increase in strain energy due to heating a cantilever to a temperature higher than the substrate, and equilibrium crack lengths are determined by equating the adhesion energy and the strain energy release rate. The equilibrium crack lengths predicted by the model agree qualitatively and are within 15% of measured crack lengths. Increased adhesion energy decreases the equilibrium crack lengths for both single and multiple pulse laser operations. The laser repair process is predicted to increase the free lengths of micromachined polysilicon cantilevers from that achieved immediately after the drying process.