Abstract
This paper presents the effects of H/sub 2/ annealing and polysilicon emitter structures on H/sub FE/ characteristics of n-p-n bipolar junction transistors. The increase of the number of H/sub 2/ annealing steps results in the device performance (H/sub FE//spl times/V/sub A/) improvement by 27.8%, due to the formation of H-Si dangling bonds, which allow the decrease of the base current. In addition, the bilayer of undoped polysilicon deposition/ion implantation and in situ doped polysilicon in the ploy emitters greatly improve the level of H/sub FE/ reliability and 1/f noise characteristic. The experimental results of H-Si dangling bond property at the polysilicon grain boundaries and polysilicon interface with the H/sub 2/ annealing steps in n-p-n bipolar junction transistor formulation will be also presented.
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