Analytical and numerical studies of the dependence of high frequency performance on the use of a polysilicon emitter in bipolar transistors

Abstract

The effects of the polysilicon emitter on the unity gain frequency ƒ T of bipolar transistors have been investigated both analytically and numerically. An analytical model for minority carrier transport in the polysilicon emitter that separately characterizes the polysilicon layer and the ultra thin oxide layer that could exist at the polysilicon/mono-crystalline silicon interface has been formulated. Using this analytical model as well as a one-dimensional numerical model, the presence of polysilicon grain boundaries was shown to degrade the high frequency performance of polysilicon emitter bipolar transistors with a clean interface as compared to that of conventional transistors with the same emitter-base junction depth. The interfacial oxide layer can either improve or degrade the transistor high frequency performance, depending on the thickness ratio of the mono-crystalline silicon emitter to the polysilicon emitter region. For a small ratio, the lower the tunnelling probability of the interfacial oxide layer the better is the improvement in ƒ T. However, if the ratio is larger the converse can be true. The thickness ratio at which the effect of the interfacial oxide layer on ƒ T reverses was foudn to depend primarily on the relative magnitudes of the minority carrier diffusion coefficients in the two emitter regions. It was also observed that for typical device designs where the mono-crystalline silicon emitter region is much thinner than the polysilicon emitter region and where a native interfacial oxide layer of ≥4 A ̊ exists, polysilicon emitter bipolar transistors are likely to have higher ƒ T's than comparable conventional transistors provided that the interfacial oxide layer is homogeneous.