Reduction of [formula omitted] noise in polysilicon emitter bipolar transistors

Abstract

Polysilicon emitter bipolar transistors are becoming common in modern bipolar and BICMOS processes. For analogue applications, it is important to understand the noise phenomena as well as the more familiar circuit behaviour. In this paper we report on experimental studies of the 1 f noise in these transistors. Firstly, we show how the noise depends strongly on the type of interfacial oxide layer at the polysilicon/silicon interface. For example, the 10 Hz noise of a device with an RCA interfacial oxide layer is approximately four times higher than that of a comparable device with an HF interfacial layer (i.e. thinner and with poorer integrity). The dependence is explained by means of a simple mathematical model of the 1 f noise generation, based on the fluctuation in the occupancy level of individual traps in the thin oxide at the polysilicon/silicon interface. Two methods are presented for reducing the noise in polysilicon emitter bipolar transistors. The first involves the use of an interface anneal, which has the effect of breaking up the interfacial layer. This method reduces the 10 Hz noise by a factor of approximately four, but also dramatically reduces the current gain. The second method involves a fluorine implantation into the polysilicon immediately after the emitter implant. This reduces the 10Hz noise by a factor of approximately three, but does not significantly alter the current gain. This is explained by the action of the fluorine in passivating surface states in the interfacial oxide layer. It is also shown how the physical emitter structure can influence the noise. Both the effective depth of the emitter-base junction and the periphery-to-area ratio have an influence on the noise through the varying significance of surface recombination currents.