Fabrication of polycrystalline silicon nanowires using conventional UV lithography

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Silicon nanowires are processed by using the sidewall spacer formation technique. This technique uses craftily a drawback of anisotropic etching to go beyond optical limits with conventional UV lithography for precision patterns. The final width of the spacer is controlled by the steepness of the etching side and by the uniformity of the wall recovering layer. In our process, a polysilicon layer is deposited by low pressure chemical vapour deposition technique on SiO2 wall network patterned by conventional UV lithography technique. Accurate control of the etching rate of the polysilicon leads to the formation of nanometric size sidewall spacers with a curvature radius below 100nm. Networks of such parallel polysilicon nanowires were electrically tested in function of temperature (530K<T<200K). Results show that conductivity of undoped polysilicon nanowire is thermally activated at high temperature (T >300K) with thermal activation EA ∼ 0.3 eV