Ultra-shallow Junctions Research Articles

Modelling of Boron Trapping at End-of-Range defects in pre-amorphized ultra-shallow junctions

In this work, the evolution of boron trapping at End-of-Range (EOR) defects was investigated by secondary ion mass spectrometry (SIMS) and transmission electron microscope (TEM). Si wafers with a constant boron concentration of 2 × 10 18 cm −3 were implanted with 30 keV germanium and with a dose of 10 15 cm −2 and then annealed at 700, 800, or 900 °C in an N 2 ambient for various times. The experimental results suggest that the evolution of boron-trapping peak is driven by the evolution of {3 1 1} defects and that the dislocation loops contribution to the trapping mechanism is less pronounced. An analytic model for the concurrent boron trapping at {3 1 1} defects and dislocation loops was developed by taking into account the geometry of the EOR defects. The trapped species is represented by neutral BI pairs which can be captured either by {3 1 1} defects or by dislocation loops. The model accurately reproduces the complex evolution of the trapping peak as a function of both the annealing time and temperature. These results confirm that the evolution of the boron-trapping peak is closely related to the evolution of the {3 1 1} defects, therefore suggesting that boron trapping is associated to the capture and release of boron atoms at the {3 1 1} defects formed in the EOR region.

Series Resistance and Mobility Extraction Method in Nanoscale MOSFETs

This paper presents a BSIM-based method for source/drain series resistance and mobility extraction in nanoscale strained-silicon metal oxide semiconductor field effect transistors (MOSFETs) with halo implants. This method is more accurate than the conventional channel-resistance and shift and ratio method because it considers the gate-length dependence of mobility caused by local uniaxial stress and laterally nonuniform channel doping. We have verified this method using samples with different stressor/doping conditions and good agreement with experimental data has been obtained. The accuracy of the Berkeley Short-channel IGFET model (BSIM) extraction method is also proven by simulated current–voltage characteristics with different external resistant values. Significant mobility degradation in the short-channel regime has been observed for various uniaxial stressors. This method may serve as a suitable process monitor tool for ultrashallow junction and strained process development.

Defect Engineering for Ultrashallow Junctions using Surfaces

The behavior of point defects within silicon can be changed significantly by controlling the chemical state at the surface. In ultrashallow junction applications for integrated circuits, such effects can be exploited to reduce transient enhanced diffusion and increase dopant activation. The present work demonstrates such effects experimentally for arsenic and boron.

Dopant Activation Phenomenon by Flash Lamp Annealing

We studied the characteristics of ultra-shallow junctions (USJ) formed by flash lamp annealing (FLA) to reveal the nature of the dopant activation. We found that FLA is a form of solid phase epitaxial regrowth(SPER), employing high temperatures and short (mili-second) times. This achieves higher dopant activation than obtained in SPER.

CMOS Scaling For the Next Decade: Trends, Challenges and Opportunities

The advent of high-k/metal gates into production for CMOS gate stacks has marked the onset of MOSFET scaling that has clearly become reliant on new materials and / or new device architecture. Additionally, new approaches to form ultra-shallow junctions with high active-dopant concentrations and low schottky barrier height silicides with novel materials to reduce contact resistance have been reported by many groups and will continue to facilitate MOSFET scaling with increasing performance. It is becoming clear that Si (as the channel) may not be able to provide for the high performance combined with low power technologies that would be needed in future. Over several years, there has been a lot of research on high mobility channels: group IV for pMOSFETs and III-V for NMOSFETs. However, there appears to be little consensus on a) the choice of high mobility channels for P and N channel MOSFETs, b) its potential compared to short channel strained-Si, and 3) potential technology node for insertion. In this work, trends, challenges and opportunities related to several of the aforementioned modules (gate stack, junctions, contacts, and high mobility Ge based channels) will be briefly presented and discussed.

High-Resolution Junction Photo-Voltage Mapping of Sheet Resistance and Leakage Current Variations with ms-Timescale Annealing Methods

A non-contact method for measurement of sheet resistance and leakage current (RsL) for ultra-shallow junction characterization is described where high-density (30,000 pixel) sheet resistance maps provide detailed evaluation of local and global variations of dopant activation arising from implant and anneal conditions. Various examples of RTP-spike, flash and laser anneals and new low-dose implant results are discussed.

Study on silicon surface oxidation of post-implant resist cleaning

Minimum substrate loss is required for resist strip of high dose, ultra shallow junction implant for source/drain extensions. Silicon surface oxidation of downstream plasma resist strip results in silicon recess of the source/drain extension regions. This paper reports the study of silicon surface oxidation for different resist strip plasma chemistries and the effect of plasma strip process parameters such as power, pressure and temperature on silicon surface oxidation. A good agreement was found between optical ellipsometry, XPS (X-ray photoelectron spectroscopy) and TEM (transmission electron spectroscopy) for thickness measurement of very thin (<20 Å) oxide grown on silicon surface due to plasma exposure. Selectivity of crust breakthrough and resist removal over silicon oxidation was also discussed in this paper along with dopant loss.

Non-melt laser annealing of Plasma Implanted Boron for ultra shallow junctions in Silicon

In this work we present results on sub-melt Excimer laser annealing in order to obtain difussionless activation of Boron for the creation of ultra shallow P-MOS devices. For the fulfillment of the strict requirements imposed by the ITRS roadmap for the 32 nm node we have implemented two emerging techniques: non-melt laser annealing and BF 3 Plasma Doping implantation (PLAD). By using PLAD, we were able to create ultra shallow and abrupt as implanted profiles. On the other hand, by performing laser annealing on the samples in the sub-melt regime, we can achieve high levels of electrical activation, while practically eliminating Boron diffusion, due to its capability to deliver low thermal budget in the sub-microsecond time scale. An Excimer KrF laser ( λ = 248 nm and pulse duration 38 ns) has been used. The post annealing characterization of the samples included SIMS and Van Der Pauw Sheet resistance measurements. SIMS data indicate almost difussionless dopant behavior with R s values at 680 Ω/sq. We have concluded our analysis with the examination of the morphological characteristics both of the surface of the sample using Atomic Force Microscopy (AFM) and the evolution of the recrystallization of the amorphized layers and the removal of the defects by means of cross-section Transmission Electron Microscopy.

The impact of nitrogen co-implantation on boron ultra-shallow junction formation and underlying physical understanding

In this paper, we show that boron transient enhanced diffusion can be reduced to different extents by varying the distribution of nitrogen atoms in the junction. This is attributed to the relative location of nitrogen atoms with respect to boron profile and end-of-range defect band, affecting the interactions between dopants and defects upon annealing. In addition, variations in boron dopant activation and deactivation are also observed. Similar to fluorine co-implantation, it is proposed that nitrogen atoms react with vacancy point defects to form nitrogen–vacancy clusters that will trap the interstitials emitted from end-of-range defects. However, we report that the interstitial sink efficiency of nitrogen atoms is not as good as the co-implanted carbon atoms, which is noticed from the dopant deactivation curves. In terms of extended defect evolution, the results clearly indicate that end-of-range defects can be stabilized by choosing the optimized co-implant condition of N. Finally, a deeper physical understanding on the diffusion/clustering pathways of nitrogen co-implantation is achieved to supplement and explain the boron diffusion and deactivation behaviors.

An a-Si:H/SiGe/Si punchthrough heterojunction phototransistors with an thin-Al film

An a-Si:H/SiGe/Si punchthrough heterojunction phototransistors (PTHPTs), responding to a wavelength of 850 nm, have been proposed and demonstrated in this work. The dramatic difference between PTHPTs and conventional heterojunction phototransistors is that the base is completely depleted in the PTHPTs, thus a larger optical gain is achieved due to the lack of a neutral base. Furthermore, the use of low-temperature a-Si:H instead of conventional crystalline silicon, a strained SiGe can be preserved at the interface of base and emitter, allowing ultrashallow junctions and abrupt doping profiles. Another advantage is that the a-Si:H can provide large valence-band discontinuity between base and emitter, avoiding photogenerated holes injected from base to emitter, and hence a larger collector current. In addition, we employed a thin Al-coating covered on the surface of emitter to enhance the collection of photogenerated holes. In comparison to the PTHPTS without the thin-Al coating, the optical gain of PTHPTs with thin-Al coating is increased from 922 to 3970 at 5-V bias voltage, responding to a light source of 850 nm with 0.028 mW.

Structural and electrical characterisation of ion-implanted strained silicon

The production of low resistance ultra-shallow junctions for e.g. source/drain extensions using low energy ion-implantation will be required for future CMOS devices [H. Wakabayashi, M. Ueki, M. Narihiro, T. Fukai, N. Ikezawa, T. Matsuda, K. Yoshida, K. Takeuchi, Y. Ochiai, T. Mogami, T. Kunio, Trans. Electron Devices 49 (2002) 89–94]. This architecture will require implants which demonstrate high electrical activation and nm range depth profiles. We investigate the properties of Sb implants in tensile strained silicon due to their potential to satisfy these criteria and the mobility enhancements associated with tensile strained silicon. Low energy (in this case 2 keV) implants coupled with Sb’s large atomic radius are capable of providing ∼10 nm implant depths. In addition to this, Sb demonstrates higher electrical activation in the presence of tensile strain, when compared with the more traditional n-type dopant As [N.S. Bennett, N.E.B. Cowern, A.J. Smith, R.M. Gwilliam, B.J. Sealy, L. O’Reilly, P.J. McNally, G. Cooke, H. Kheyrandish, Appl. Phys. Lett. 89 (2006) 182122]. We now report on the initial results of an ongoing systematic study over a wide silicon tensile strain range (from 0.4% to 1.25% strain) in order to establish clear strain-related trends. Graded Si 1− x Ge x virtual substrates (VS) with 0.1 ≤ x ≤ 0.3 were used as template substrates upon which tensile Si layers were grown. Prior to implantation the quality of the strained layer and SiGe buffer is assessed using UV micro-Raman spectroscopy (μRS), synchrotron X-ray topography (SXRT) and high-resolution X-ray diffraction (HR-XRD). For measurements of strain following implantation, HR-XRD is found to be more useful than μRS because of additional carrier-concentration induced Si Raman peak shifts. These shifts obscure small changes in the strain state, and are a result of the degenerate doping levels achieved in these samples (∼7 × 10 20 cm −3). Using X-ray techniques, at Ge concentrations >23% (i.e. ɛ > 0.9%) we find clear evidence of tilt in the SiGe VS, which impacts on the quality of the strained Si. Additionally, stacking faults have been detected non-destructively in the higher strain samples ( ɛ = 1.25%, VS = Si 0.7Ge 0.3) using SXRT in transmission mode.

Advanced activation trends for boron and arsenic by combinations of single, multiple flash anneals and spike rapid thermal annealing

Millisecond annealing as an equipment technology provides temperature profiles which favour dopant activation but nearly eliminate dopant diffusion to form extremely shallow, highly electrically activated junctions. For the 45-nm technology node and beyond, precisely controlled gate under-diffusion is required for optimum device performance. Therefore, on boron and arsenic beamline-implanted wafers, various annealing schemes were investigated for the formation of ultra-shallow and custom-shaped junctions. The main scheme consisted of flash annealing with peak temperatures ranging from 1250 to 1300 °C, combined with spike rapid thermal annealing with peak temperatures in the range from 900 to 1000 °C to achieve a desired junction depth. As alternative, to reduce the sheet resistance of pMOS and nMOS source–drain extensions, combinations of two or three flash anneals in succession were tested. Finally, the standard flash anneal condition of a 750 °C intermediate temperature followed by the flash anneal was changed to a high intermediate temperature of 950 °C followed by the flash anneal up to 1300 °C. The results of all these annealing schemes were analysed by four-point probe measurement. Selected samples were analysed by Hall-effect measurements for peak activation, and by secondary ion mass spectrometry for profile shape as well as diffusion effects. Transmission electron microscopy was used to study residual defects. Selected boron and arsenic dopant profiles were also compared to predictive simulation results which address the diffusion and activation at extrinsic concentrations.

Evidence of the carrier mobility degradation in highly B-doped ultra-shallow junctions by Hall effect measurements

In this paper, we present an empirical method for the self-consistent interpretation of SIMS and Hall effect measurements of boron-doped ultra-shallow junctions that allows to estimate the activation level of the doped layers (maximum active dopant concentration, active dose fraction) and, for the case of partially activated structures, to assess whether or not the carrier mobility is affected by the electrically inactive BICs. Epitaxial structures realized by chemical vapour deposition (CVD) were studied. We found that, for partially electrically active structures, a degradation of the drift mobility due to the presence of BICs is shown, which is experimentally confirmed by low temperature Hall effect measurements, indicating the existence of an additional Coulomb-type scattering mechanism. In addition, the post-deposition annealing steps (either 1050 °C spike or 1300 °C flash) are found to improve the activation level and induce a corresponding improvement of the carrier mobility, which is clearly associated to the progressive dissolution of the BICs during annealing.

Atomistic modeling of F nV m complexes in pre-amorphized Si

The co-implantation of F and B in pre-amorphized Si has been proved to be beneficial for the fabrication of ultrashallow junctions due to a remarkable reduction of B diffusion. This is attributed to the presence of fluorine-vacancy (F–V) complexes after regrowth, acting as annihilation centers for Si interstitials. Whereas the resulting F profile in the recrystallized layer can be easily determined by chemical profiling, the vacancy distribution, which has a strong influence on B diffusion, can only be indirectly estimated. In this work, atomistic simulations have been used to analyze several aspects that can affect the efficiency of F–V complexes on Si interstitials annihilation, by considering the effects on B diffusion and the evolution of F profiles. The vacancy content of the complexes, determined by the F/V ratio, and the complex size play an important role on B redistribution. The existence of a recombination barrier for the interaction of a Si interstitial and some F–V complexes, as proposed by theoretical calculations, and its influence on the Si interstitial annihilation efficiency of the complexes are also analyzed.

High thermal stability of vacancy clusters formed in MeV Si-self-ion-implanted Si

We have shown that considerable vacancy defects, introduced by MeV Si self-ion implantation, can survive a 900°C∕5min annealing for gate formation. By analyzing the trap-limited Si interstitial diffusion, we have characterized these vacancy clusters. Furthermore, we show that the remaining vacancies are sufficient to reduce B diffusion. The study suggests that MeV ion implantation, a promising approach for ultrashallow junction formation in metal-oxide-semiconductor device fabrication, can be inserted before gate formation (involving high temperature annealing) to avoid irradiation damage on gate structures.

Micro-four-point probe Hall effect measurement method

We report a new microscale Hall effect measurement method for characterization of semiconductor thin films without need for conventional Hall effect geometries and metal contact pads. We derive the electrostatic potential resulting from current flow in a conductive filamentary sheet with insulating barriers and with a magnetic field applied normal to the plane of the sheet. Based on this potential, analytical expressions for the measured four-point resistance in presence of a magnetic field are derived for several simple sample geometries. We show how the sheet resistance and Hall effect contributions may be separated using dual configuration measurements. The method differs from conventional van der Pauw measurements since the probe pins are placed in the interior of the sample region, not just on the perimeter. We experimentally verify the method by micro-four-point probe measurements on ultrashallow junctions in silicon and germanium. On a cleaved silicon ultrashallow junction sample we determine carrier mobility, sheet carrier density, and sheet resistance from micro-four-point probe measurements under various experimental conditions, and show with these conditions reproducibility within less than 1.5%.

Physically based kinetic Monte Carlo modeling of arsenic-interstitial interaction and arsenic uphill diffusion during ultrashallow junction formation

A kinetic arsenic-interstitial interaction model has been developed to study and predict arsenic transient enhanced diffusion (TED) and deactivation behavior during ultrashallow junction (USJ) formation. This model is based on density functional theory and has been verified by previous experiments in which the significant role of interstitial mechanism in arsenic TED was revealed. The mechanism of enhanced and retarded arsenic diffusion in different point defect environments is investigated by utilizing this model in kinetic Monte Carlo simulation. The arsenic-interstitial pair, with low binding energy and low migration energy, is shown to be the major contributor to arsenic TED in silicon interstitial-rich situations. In addition, by using this model, we demonstrate the transient existence of arsenic-interstitial clusters (AsnIm) during postimplant annealing and propose their possible role in deactivation for short time annealings such as laser annealing and spike annealing. Moreover, we have developed a novel surface-trap based kinetic Monte Carlo model to simulate arsenic uphill diffusion in proximity of the Si∕SiO2 interface. The simulation results show that the activation behavior of the uphill portion of arsenic has considerable impact on the junction sheet resistance. The activation behavior of this arsenic is expected to become more important when USJ depth is scaled down further.

Si/SiGe heterostructures for advanced microelectronic devices

The permanent size reduction and increasing complexity of microelectronic structures is accompanied by drastic requirements on ultra-thin layer quality. This is the case for Si x Ge1− x ultra-shallow junctions and locally doped nanostructures such as quantum wells, wires or dots. For example, the new generation of Si/Si x Ge1− x -based micro- and optoelectronic devices, e.g. velocity modulation field effect transistor, resonant tunnelling diode, single electron transistor, requires accurate control of surface and interface roughness, almost 0-defect structures and very sharp doping profiles in both p- and n-type material. There exist several difficulties. The first one is the strain control and adjustment (from fully strained to fully relaxed 2D and 3D nanostructures), which also determines the morphological evolution of thin Si1− x Ge x layers and the development of growth instability. The second problem is the doping redistribution during growth, which combines thermodynamics (driving force) and kinetics (exchange rate) mechanisms. The third problem is the 0-defect requirement for ultra-thin doped junctions. In this article, we give an overview of the new insights obtained during the last years in these three domains and we present the physical properties of the structures realised.

Tunneling mechanism of GaAs ultrashallow sidewall tunnel junction

AbstractConductance‐voltage (G ‐V) and current‐voltage (J ‐V) measurements were applied to reveal the tunneling mechanisms of GaAs ultra‐shallow sidewall tunnel junctions, which were fabricated by molecular layer epitaxy. From the G ‐V results, peaks were detected at 2, 12 and 14 THz at 6 K. In the J ‐V measurements, the fine structure near the peak voltage and a step in the tunneling current in the negative resistance region can also be observed. The tunneling mechanism is discussed in terms of the band transition, deep level and phonon‐assisted tunneling. (© 2008 WILEY‐VCH Verlag GmbH &amp; Co. KGaA, Weinheim)

1-nm Spatial Resolution in Carrier Profiling of Ultrashallow Junctions by Scanning Spreading Resistance Microscopy

Recently, we reported significantly improved spatial resolution in scanning spreading resistance microscopy (SSRM) by measuring in a vacuum. In this paper, we demonstrate the 1-nm spatial resolution of SSRM in carrier profiling by comparing with the 3-D device simulation. The simulation results show that the accuracy of ultrashallow-junction delineation depends on the effective radius of the probe. The precisely measured junction depth corresponds to an effective probe radius of 0.5 nm. We attribute the high resolution to the elimination of parasitic resistances of the whole measuring circuit. Application to failure analysis of n-type metal-oxide-semiconductor field-effect transistors clarified the impact of halo-carrier profiles on Vth-roll-off characteristics.