Advanced activation trends for boron and arsenic by combinations of single, multiple flash anneals and spike rapid thermal annealing

Abstract

Millisecond annealing as an equipment technology provides temperature profiles which favour dopant activation but nearly eliminate dopant diffusion to form extremely shallow, highly electrically activated junctions. For the 45-nm technology node and beyond, precisely controlled gate under-diffusion is required for optimum device performance. Therefore, on boron and arsenic beamline-implanted wafers, various annealing schemes were investigated for the formation of ultra-shallow and custom-shaped junctions. The main scheme consisted of flash annealing with peak temperatures ranging from 1250 to 1300 °C, combined with spike rapid thermal annealing with peak temperatures in the range from 900 to 1000 °C to achieve a desired junction depth. As alternative, to reduce the sheet resistance of pMOS and nMOS source–drain extensions, combinations of two or three flash anneals in succession were tested. Finally, the standard flash anneal condition of a 750 °C intermediate temperature followed by the flash anneal was changed to a high intermediate temperature of 950 °C followed by the flash anneal up to 1300 °C. The results of all these annealing schemes were analysed by four-point probe measurement. Selected samples were analysed by Hall-effect measurements for peak activation, and by secondary ion mass spectrometry for profile shape as well as diffusion effects. Transmission electron microscopy was used to study residual defects. Selected boron and arsenic dopant profiles were also compared to predictive simulation results which address the diffusion and activation at extrinsic concentrations.