Ultra Large Scale Integration Research Articles

Corrosion of electrodeposited copper by exposure to volatile organic compounds

In this paper we investigate the corrosive behaviour of various volatile organic compounds (VOCs) on electroplated copper. The VOCs we considered were of the following types: (i) aromatic and substituted-aromatic compounds (benzene, toluene and ethyl benzene); (ii) a chlorine-substituted hydrocarbon (dichloromethane) and (iii) an aliphatic alcohol (isopropyl alcohol). Contamination by VOCs is typical of ULSI (Ultra Large Scale Integration) manufacturing environments, and exposure of Cu to VOC-contaminated clean room air has been pinpointed as a serious cause of interconnects failure. SEM observation highlighted corrosion signature that are typical of the different classes of molecules. In particular, the corrosion of copper is almost absent following exposure to isopropyl alcohol, very slow in the case of aromatic molecules and severe in the case of dichloromethane. The obtained results can be interpreted in terms of a crevice corrosion mechanism under droplets, enhanced by pitting in the presence of chlorinated solvents.

Effect of liquid additives in supercritical fluid deposition of copper for enhancing deposition chemistry

Four liquid chemical reagents (ethanol, 2-propanol, hydrogen peroxide, and formic acid) were evaluated as reducing agents for supercritical fluid deposition of Cu (Cu-SCFD) using bis(2,2,6,6-tetramethyl-3,5-heptanedionato)copper as a precursor onto a Ru-coated Si substrate for ultra large scale integration metallization. Deposition was carried out using a batch-type reactor and heating the substrate from 40 °C to 250 °C at a rate of 4.5 °C/min. 2-propanol and hydrogen peroxide yielded Cu grains, but not a continuous Cu film. Only formic acid yielded a high-purity continuous film. Solvent effect of two chemical reagents (ethanol and 2-propanol) on Cu-SCFD with H 2 as a reducing agent was also investigated by using in situ method, in which optical reflectivity of growing surface at wavelength of 770 nm was used. Ethanol addition enhanced the deposition reaction without degrading both the surface morphology and high purity of the deposited Cu film.

Characteristics of Spontaneous Reaction Occurred by Metal Contamination and Silicon Substrate for Ultralarge-Scale Integration Semiconductor Process

Heavy metals such as Cu, Fe, and Ni are well known to cause defects in Si substrate and to degrade thin oxide quality in ultralarge-scale integration (ULSI) circuits. This degradation can seriously reduce yield and long-term reliability, which are the two critical factors in ULSI manufacturing. Metallic contamination originates in such process materials as gases and wet chemicals. As devices shrink, microcontamination is having an increasingly negative effect on operation function and yield. Semiconductor manufacturers can markedly increase wafer yield by reducing contamination. This work analyzes the contamination of processed wafers by heavy metals before the deposition of gate oxide. Many bamboo-shoot-like defects are present on the wafer edge. Additionally, many pits are also formed in the active region of a device when silicon substrate suffers from heavy metallic contamination. Transmission electron microscopy (TEM) and energy dispersive spectroscopy (EDS) are adopted to study the bamboo-shoot-like defects and pit defects. A possible mechanism was identified to explain the problem stage in manufacturing process. This work demonstrates the spontaneous dissolution of the contaminating metal in the silicon substrate. Tiny pits are becoming a serious problem in the manufacturing of submicrometer and deep-submicrometer ULSIs , which always suffer from yield loss at the wafer edge because of bamboo-shoot-like defects that are associated with design rule limitations. A detailed analysis and process flow check reveal that metal contamination generates tiny pits around the wafer edge in the raw material wafer process flow. These tiny pits result in bamboo-shoot-like defects in the non-o.d. (periphery) region and pits in the o.d. (active) region. These two defects cause failure of the device because of leakage. This work is the first to describe this issue regarding ULSI manufacturing and demonstrates that tiny pits represent high risk of device operation at the deep submicron level. An effective solution is to more strictly limit the degree of metallic contamination.

Effects of Molybdate Concentration on the Characteristics of Ni – Mo – P Diffusion Barriers Grown by Nonisothermal Electroless Deposition

Ternary Ni-based amorphous films can serve as a barrier layer for Cu interconnects in ultralarge-scale integration (ULSI) applications. In this paper, films deposited on silicon wafers without a complicated pretreatment such as Pd activation were prepared using a nonisothermal deposition (NITD) method. The deposition solutions and operating conditions for preparing the alloys are presented, and the effect of the concentration of added in electrolytes on the deposition rate is investigated. The surface morphology, microstructures, compositions, and electrical resistivity of the deposits are also thoroughly examined. Based on the experimental results, the Ni-based ternary alloys produced by the NITD method contain high levels of both Mo and P, and the properties of films are dependent on the concentration of molybdate in electrolytes. It is concluded that the thin films produced by the proposed approach in this study are promising for the technologies in ULSI.

Characterization of Self-Formed Ti-Rich Interface Layers in Cu(Ti)/Low-k Samples

In our previous studies, thin Ti-rich diffusion barrier layers were found to be formed at the interface between Cu(Ti) films and SiO2/Si substrates after annealing at elevated temperatures. This technique was called self-formation of the diffusion barrier, and is attractive for fabrication of ultralarge-scale integrated (ULSI) interconnects. In the present study, we investigated the applicability of this technique to Cu(Ti) alloy films which were deposited on low dielectric constant (low-k) materials (SiOxCy), SiCO, and SiCN dielectric layers, which are potential dielectric layers for future ULSI Si devices. The microstructures were analyzed by transmission electron microscopy (TEM) and secondary-ion mass spectrometry (SIMS), and correlated with the electrical properties of the Cu(Ti) films. It was concluded that the Ti-rich interface layers were formed in all the Cu(Ti)/dielectric-layer samples. The primary factor to control the composition of the self-formed Ti-rich interface layers was the C concentration in the dielectric layers rather than the enthalpy of formation of the Ti compounds (TiC, TiSi, and TiN). Crystalline TiC was formed on the dielectric layers with a C concentration higher than 17 at.%.

Stress-induced voiding study in integrated circuit interconnects

An analytical equation for an ultralarge-scale integration interconnect lifetime due to stress-induced voiding (SIV) is derived from the energy perspective. It is shown that the SIV lifetime is strongly dependent on the passivation quality at the cap layer/interconnect interface, the confinement effect by the surrounding materials to the interconnects, and the available diffusion paths in the interconnects. Contrary to the traditional power-law creep model, we find that the temperature exponent in SIV lifetime formulation is determined by the available diffusion paths for the interconnect atoms and the interconnect geometries. The critical temperature for the SIV is found to be independent of passivation integrity and dielectric confinement effect. Actual stress-free temperature (SFT) during the SIV process is also found to be different from the dielectric/cap layer deposition temperature or the final annealing temperature of the metallization, and it can be evaluated analytically once the activation energy, temperature exponent and critical temperature are determined experimentally. The smaller actual SFT indicates that a strong stress relaxation occurs before the high temperature storage test. Our results show that our SIV lifetime model can be used to predict the SIV lifetime in nano-interconnects.

Synthesis and characterization of electroless deposited Co–W–P thin films as diffusion barrier layer

Selective barriers against copper diffusion deposited by electroless reaction are interesting in term of electromigration. In this article, the barrier layer of cobalt–tungsten–phosphorus (Co–W–P) alloy was electroless deposited onto copper substrates for ultra large scale integration (ULSI) applications. The Co–W–P thin film was formed directly on copper, without a palladium catalyst, from citrate plating baths with sodium hypophosphite as reducing agents. The influence of tungsten addition on the barrier properties has been studied and the optimum conditions to obtain films with the highest oxidation protection have been determined. Co–W–P layer properties such as chemical composition, surface morphology, and phase structure and corrosion behavior have been investigated. The deposited CoWP layer showed higher oxidation and corrosion resistance and soft magnetic behavior.

Evaluation of New Amorphous Hydrocarbon Film for Copper Barrier Dielectric Film in Low-k Copper Metallization

In recent ultra large-scale integration (ULSI), Cu wiring and low-k dielectrics are used to reduce resistive capacitive (RC) delay in interconnects. Cu diffusion barrier layers, such as SiC and SiCN, have relatively high k-values, thus they decrease effective k-values (keff) of dielectrics. For this issue, we propose a new amorphous hydrocarbon film (a-CHx) as a Cu barrier dielectric deposited using a microwave-excited plasma reactor with a showerhead. Low ion bombardments and optimum deposition gases gave an excellent film, which achieved low leakage current and thermal resistance simultaneously. This film showed Cu diffusion barrier ability at 350 °C and a lifetime of more than 10 years lifetime at 0.2 MV/cm, which is sufficient for next-generation interlayer dielectric films.

Low-Dielectric-Constant Nonporous Fluorocarbon Films for Interlayer Dielectric

Low-dielectric-constant (k<2.0) nonporous fluorocarbon films are formed using a new microwave-excited low electron temperature and high-density plasma system with a dual-shower-plate structure. In the new system, the material gas (C5F8) is supplied by a lower shower plate inserted in the diffusion plasma region of very low electron temperature (around 1–2 eV). An upper shower plate is used for supplying the plasma excitation gas in a uniform downflow in the chamber. Since such a gas flow pattern can prevent the penetration of the material gas into the plasma excitation region, the overdecomposition of the material gas can be markedly suppressed as compared with that in the case of using conventional plasma systems such as an electron cyclotron resonance (ECR) plasma source. As a result, fluorocarbon films can be formed by maximizing the original characteristics of material gases. The fluorocarbon films formed using the new system have not only low k but also low leakage current density, sufficient mechanical strength, strong adhesion, high heat resistance and good surface smoothness. Therefore, such films can be used in interlayer dielectrics in ultralarge-scale integration (ULSI) devices.

Extrasmall-Area Three-Dimensional Solenoid-Shaped Inductor Integrated into High-Speed Signal Processing Complementary Metal–Oxide–Semiconductor Ultralarge-Scale Integrated Circuits

Using fine-pitched ultralarge-scale integrated (ULSI) circuit local interconnects, an extrasmall-area, three-dimensional (3-D) solenoid-shaped inductor is developed for scaled-down high-speed logic LSIs. The 3-D solenoid inductor has a four-layered solenoid structure with fine-pitched local low-k/Cu interconnects, achieving an area reduction from 1/6 to 1/10 of the area of a conventional monolayer-spiral inductor using wide-pitched global interconnects. The small area also suppresses the crosstalk due to the compaction of the magnetic field around the inductor. The 3-D solenoid structure has a higher self-resonant frequency than a stacked-spiral inductor of the same area or the same inductance due to a small effective parasitic capacitance. A 20 Gb/s D-type flip-flop (D-F/F) using the 3-D solenoid inductor for peeking demonstrated a smaller degree of jitter than that using a monolayer-spiral inductor under a 1 V power supply. The 3-D solenoid inductor is a key component for scaled-down high-speed logic LSIs with a low power supply voltage.

용액 교반이 미세 패턴 내 무전해 구리 도금에 미치는 영향

The effect of solution agitation on the copper electroless deposition process of ULSI (ultra large scale integration) interconnections was investigated by using physical, electrochemical and electrical techniques. It was found that proper solution agitation was effective to obtain superconformal copper configuration within the trenches of <TEX>$130{\sim}80nm$</TEX> width. The transition of open potential during electroless deposition process showed that solution agitation induced compact structure of copper deposits by suppressing mass transfer of cuprous ions toward substrate. Also, the specific resistivity of copper layers was lowered by increasing agitation speed, which made the deposited copper particles smaller. Considering both copper deposit configuration and electric property, around 500 rpm of solution agitation was the most suitable for the homogeneous electroless copper filling within the ultra-fine patterns.

In situ Observation of Initial Nucleation and Growth Processes in Supercritical Fluid Deposition of Copper

The initial nucleation and coalescence of Cu by supercritical fluid deposition (SCFD) were monitored by measuring the surface reflectivity of visible white light. The reflectivity at 770 nm is sensitive to initial nucleation, thus, the nucleation and coalescence temperatures of Cu-SCFD can be easily monitored by this in situ technique. The nucleation temperature of Cu-SCFD was found to be independent of the precursor concentration, which suggests a strong adsorption and surface saturation of the source precursor at high concentration. A high H2 concentration up to 0.39 mol/L with Cu(tmhd)2 as a precursor can decrease the nucleation temperature from 215 to 180 °C. A high H2 concentration is also effective for realizing a smooth surface morphology of the deposited Cu film and for making the film thin at the coalescence stage probably because of the initial nucleation with a high number density. The fabrication of a 10-nm-thick continuous Cu film, which is required as a seed layer in ultralarge scale integration (ULSI), was successfully demonstrated with a high H2 concentration of 0.39 mol/L.

Investigation of Zr–Si–N∕Zr bilayered film as diffusion barrier for Cu ultralarge scale integration metallization

The effectiveness of ZrSiN∕Zr bilayered films to serve as diffusion barriers in Cu∕Si contacts has been investigated. Annealing studies for Cu∕ZrSiN∕Zr∕Si contact systems were carried out in N2∕H2(10%) ambient. X-ray diffraction data suggest that Cu film has preferential (111) crystal orientation and Cu silicide cannot be observed up to 700°C. Scanning electron microscopy micrographs show that the Cu film was integrated and free from agglomeration after annealing at 700°C. Auger electron spectroscopy depth profiles of the Cu∕ZrSiN(10nm)∕Zr(20nm)∕Si samples have no noticeable change except Zr silicide grows with annealing temperature up to 700°C. The results indicate excellent barrier property for ZrSiN(10nm)∕Zr(20nm) bilayer structure for Cu metallization.

Self-formation of Ti-rich Layers at Cu(Ti)/low-k Interfaces

ABSTRACTIn our previous studies, thin Ti-rich diffusion barrier layers were found to be formed at the interface between Cu(Ti) films and SiO2/Si substrates after annealing at elevated temperatures. This technique was called “self-formation of the diffusion barrier,” which is attractive for fabrication of ultra-large scale integrated (ULSI) interconnects. In the present study, we investigated the applicability of this technique to Cu(Ti) alloy films which were deposited on the four low dielectric constant (low-k) dielectric layers which are potential dielectric layers of future ULSI-Si devices. The microstructures were analyzed by transmission electron microscopy (TEM) and secondary ion mass spectrometry (SIMS), and correlated with the electrical properties of the Cu(Ti) films. It was concluded that the Ti-rich interface layers were formed in all the Cu(Ti)/dielectric-layer samples. The primary factor to control composition of the self-formed Ti-rich interface layers was the C concentration in the dielectric layers rather than the formation enthalpy of the Ti compounds (TiC and TiSi). Crystalline TiC was formed on the dielectric layers with a C concentration higher than 17 at.%.

Oxidation of Polycrystalline Copper Thin Films at Ambient Conditions

Qualitative and quantitative studies of the oxidation of polycrystalline copper (Cu) thin films upon exposure to ambient air conditions for long periods (on the order of several months) are reported in this work. Thin films of Cu, prepared by thermal evaporation, were analyzed by means of X-ray photoelectron spectroscopy (XPS) to gain an understanding on the growth mechanism of the surface oxide layer. Analysis of high-resolution Cu LMM, Cu2p3/2, and O1s spectra was used to follow the time dependence of individual oxide overlayer thicknesses as well as the overall oxide composite thickness. Transmission electron microscopy (TEM) and spectroscopic ellipsometry (SE) were used to confirm the results obtained from XPS measurements. Three main stages of copper oxide growth were observed: (a) the formation of a Cu2O layer, most likely due to Cu metal ionic transport toward the oxide−oxygen interface, (b) the formation of a Cu(OH)2 metastable overlayer, due to the interactions of Cu ions with hydroxyl groups present at the surface, and (c) the transformation of the Cu(OH)2 metastable phase to a more stable CuO layer. These three stages were found to occur simultaneously and to be mutually dependent on each other. The findings of this study may provide guidance in choosing the optimal conditions to fabricate and store copper-based ultra-large-scale integrated (ULSI) circuits.

Ultrathin Ni–Mo–P Diffusion Barriers Deposited Using Nonisothermal Deposition Method in Acid Bath

The performance and thermal stability of the ultrathin nickel-molybdenum-phosphorus (Ni-Mo-P) barrier layer deposited by the nonisothermal deposition method in acid electroless bath have been clearly investigated. The as-deposited Ni-Mo-P film (15 nm) has a low resistivity, contains high amounts of Mo (6.7 atom %) and P (25 atom %), and has an amorphous structure. The barrier capability of this Ni-Mo-P film remains stable up to 650°C for 1 h annealing. This reveals that the resistance of Ni-Mo-P barrier film against Cu diffusion is very prominent, and this method for depositing Ni-Mo-P films is extremely promising for ultralargescale integration application.

Influence of Ta-based Diffusion Barriers on the Microstructure of Copper Thin Films

Copper represents the most commonly used interconnect material in ultra large-scale integration (ULSI) technology. Given that the successful implementation of Cu requires the use of underlying diffusion barriers, these studies were focused on the influence of Ta-based barrier layers on the microstructure of physical vapor deposited (PVD) and electrochemically deposited (ECD) Cu thin films. The variation of a-Ta, b-Ta, TaSiN, and TaN as an underlayer caused a modification of the PVD Cu seed-layer texture, which also affected the microstructure of Cu electroplated on top of the seed layer, both before and after recrystallization at room temperature.

Development of Step-and-Scan-Type XY-Stage System for Electron Beam Systems

The trend towards minimization in ultralarge-scale integration (ULSI) fabrication requires an increasingly precise motion accuracy for an XY-stage in a high-vacuum environment of electron beam (e-beam) systems. Aerostatic bearings allow for an extremely smooth motion, because the slider of the XY-stage is supported by an air film under a noncontact condition. However, such an XY-stage in aerostatic bearings is not easily introduced into the e-beam systems because of the markedly high amount of exhaust gas leaking into a vacuum chamber. In this paper, we describe a newly developed hybrid XY-stage guided by aerostatic bearings equipped with a noncontact seal mechanism for scanning motion and by mechanical rolling guides for stepping motion.

Revisit to the finite element modeling of electromigration for narrow interconnects

Electromigration (EM) is an important reliability concern in ultralarge-scale integration interconnects. A refined EM model based on a driving force approach is proposed in this work. The distribution of atomic flux divergence is computed by an finite element method to predict the void nucleation site in interconnects. It is demonstrated that the proposed model is more accurate than the conventional counterpart for narrow interconnects. The validity of the proposed model is verified through the study of the reservoir effect in EM. The predicted critical reservoir length agrees well with the reported values.

Low-Temperature Polysilicon History and A CPU with an Operating Frequency in the GHz Range

Research on LTPS (low-temperature polysilicon) technology proceeded from the early 1980s together with the development of laser devices. At present, in 2007, technology for manufacturing a high-performance semiconductor film on glass is already being put into practice. In this paper, I would like to discuss the history of LTPS and the development of CGS (continuous-grain silicon) technology which enabled the realization of system-on-glass technology. In addition, I will compare the characteristics of ULSI (ultra-large-scale integration) on silicon and UTFTs (ultra-thin film transistors) on glass and talk about their potential for application to various devices.