Ultra Large Scale Integration Research Articles

Improvement of Silicon-Based Thin Film Transistor Performances by Modifying Technological Fabrication Process Steps: a Similar Approach with ULSI Technology

The silicon based thin film transistors technological process evolution is governed by electrical performance improvements that are needed for the numerous fields of large area electronic applications. In fact, the electrical properties of the TFTs are directly linked to many aspects combining efforts to improve the process steps by several ways. All these approaches are similar to the ultra large scale integration technology (ULSI) ones. The goal of this paper is to highlight these similarities. After the presentation of the evolution during the last twenty years of the TFT processes, we will discuss on the common approaches between nano- and giga- electronics in order to show that their basic scientific principles are roughly the same.

Behavior of Reaction Products during Puddle Development in Fabrication of Ultralarge-Scale Integrations

The behavior of reaction products during puddle development was investigated in ultralarge-scale integration (ULSI) lithography. The concentration of reaction products originating from novolak photoresist was optically measured. Reaction products during puddle development migrated with time and gathered into cell-like structures. After from the developer puddle formation, the dissolution rate of photoresist at the cellular structures was about 10% lower than that in other areas. We examined two modified methods of puddle development in order to control the gathering phenomenon of reaction products: one is a method of agitating the reaction product by rocking the wafer, and the other is a method of heating the upper side of the developer solution. The distributions of the dissolution rate for the former and latter methods were 5.9 and , respectively. Compared with the distribution of the dissolution rate of for conventional puddle development, both modified methods can improve the distribution of the dissolution rate. The migration of reaction products was large when the wafer temperature was high, and the Marangoni number was consistent with the critical value. Therefore, the cellular structures seem to be caused by Marangoni convection.

Maintaining Cu metal integrity on low-k IMDs with a nanometer thick a-SiC:H film obtained by HWCVD

Hydrogenated amorphous silicon carbon (a-SiC:H) ultra thin films obtained by Hot wire chemical vapor deposition (HWCVD) have been shown to act as efficient diffusion barriers for copper on inter metal dielectric (IMD) layers which are of great significance for ultra-large scale integration (ULSI) circuits. In this work, we have studied the influence of the a-SiC:H barrier layer obtained by HWCVD which has implications towards issues related to the resistance to electromigration of Cu in the low dielectric (low- k) hydrogen silsesquioxane (HSQ) film. The presence of the ultra thin a-SiC:H film maintains the integrity of the Cu metal not only by suppressing Cu diffusion but also by increasing its crystallinity, which would have implications with respect to the mean time to failure (MTF) arising from metal electromigration. Though, we demonstrate this aspect on the low- k (HSQ)/Cu system, this should yield similar benefits for other low- k dielectric materials too.

Crystal Plasticity Analysis of Dislocation Accumulation in ULSI Cells with Consideration of Temperature Dependence of the Lattice Friction Stress for Silicon

Representative length scale of ULSI (Ultra Large Scale Integration) cells is going to be at a nano-meter order, and the atomic level defects, such as uneven oxide films or dislocation accumulation are becoming more and more important. Among these defects, dislocation accumulation is known to be caused by thermo-plastic deformation in silicon during the processes of device fabrication. In this study, we analyse such thermal stress, plastic slip deformation and accumulation of dislocations in STI (Shallow Trench Isolation) type ULSI devices when the temperature drops from the initial at 1000 °C to room temperature. For the analysis, we use a crystal plasticity analysis code CLP, assuming that lattice friction stress for the movement of dislocations is proportional to the hardness of silicon, which is known to have strong dependency on temperature. The results show that dislocations are generated between the temperature range from 880 to 800 °C, and its maximum density is highly dependent on the lattice friction stress in the temperature range above 800 °C. For example, the difference of 16 MPa in the lattice friction stress at 1000 °C caused increase in dislocation density more than ten times. It is concluded that control of lattice friction stress at high temperatures is one of the most promising way for the suppression of dislocation accumulation.

Electromigration characteristics in dual-damascene copper interconnects by difference of via structures

In order to improve the interconnect performance, copper has been used as the interconnect material instead of aluminum. One of the advantages of using copper interconnects instead of aluminum is better electromigration (EM) performance and lower resistance for ultralarge-scale integrated (ULSI) circuits. Dual-damascene processes use different approaches at the via bottom for lowering the via resistance. In this study, the effect of a Ta/TaN diffusion barrier on the reliability and on the electrical performance of copper dual-damascene interconnects was investigated. A higher EM performance in copper dual-damascene structures was obtained in barrier contact via (BCV) interconnect structures with a Ta/TaN barrier layer, while a lower EM performance was observed in direct contact via (DCV) interconnect structures with a bottomless process, although DCV structures had lower via resistance compared to BCV structures. The EM failures in BCV interconnect structures were formed at the via, while those in DCV interconnect structures were formed in the copper line. The existence of a barrier layer at the via bottom was related to the difference of EM failure modes. It was confirmed that the difference in EM characteristics was explained to be due to the fact that the barrier layer at the via bottom enhanced the back stress in the copper line.

전해 도금을 이용한 기가급 소자용 구리배선 공정

반도체 소자의 고속화, 고집적화, 고신뢰성화에 대한 요구는 알루미늄 합금으로부터 구리로의 배선 물질의 변화를 유도하였다. 낮은 비저항과 높은 내열화성을 특징으로 하는 구리는 그 전기적, 재료적 특성이 알루미늄과 상이하여 배선 형성에 있어 새로운 주변 재료와 공법을 필요로 한다. 본 총설에서는 상감공정(damascene process)을 사용하는 다층 구리 배선 공정에 있어 핵심이 되는 구리 전해 도금(electrodeposition) 공정을 중심으로 확산 방지막(diffusion barrier) 및 도전층(seed layer), 바닥 차오름(bottom-up filling)을 위한 전해/무전해 도금용 유기 첨가제, 화학적 기계적 평탄화(chemical mechanical polishing) 및 표면 보호막(capping layer) 기술 등의 금속화 공정에 대한 개요와 개발 이슈를 소개하고 최근의 연구 결과를 통해 구리 배선 공정의 최신 연구 동향을 소개하였다. The transition of interconnection metal from aluminum alloy to copper has been introduced to meet the requirements of high speed, ultra-large scale integration, and high reliability of the semiconductor device. Since copper, which has low electrical resistivity and high resistance to degradation, has different electrical and material characteristics compared to aluminum alloy, new related materials and processes are needed to successfully fabricate the copper interconnection. In this review, some important factors of multilevel copper damascene process have been surveyed such as diffusion barrier, seed layer, organic additives for bottom-up electro/electroless deposition, chemical mechanical polishing, and capping layer to introduce the related issues and recent research trends on them.

Thermal furnace and Ultraviolet assisted curing impact on SiOCH spin-on ultra low dielectric constant materials

In recent years, the continuous progression of ultra-large scale integration has driven the emergence of technological solutions. In particular, major challenges have been faced for the fabrication of interconnect structures, where ultra low dielectric constants are required to decrease the parasitic capacitances between metal lines. Porous material, obtained using the porogen approach, is the main candidate investigated. The curing process is critical for achieving a good control of final film structure. The integration of such material requires a good chemical and mechanical stability, particularly to maintain the structure integrity during the stressing steps: chemical mechanical polishing and packaging. In this work, Ultraviolet assisted thermal cure (or UV curing) is investigated as an alternative solution to the conventional thermal curing. Chemical and physical analyses reveal that the best porogen removal efficiency and the enhancement of matrix crosslinking are achieved when the material is UV cured. This crosslinking improvement (as indicated by higher Si–O–Si bond density in the fourier transformed infra-red spectra) can be correlated to better mechanical properties. Significantly better electrical properties (dielectric constant, leakage current and breakdown voltage) are obtained with better integrity (no moisture uptake after 1 week storage in humid atmosphere 85 °C/85% relative humidity) when the dielectric is optimally cured. Porosity evaluation reveals similar results between both curing processes with slightly larger pore size in the case of the UV cured film. Finally, a basic model is described to illustrate how the UV assisted thermal cure may improve the crosslinking in comparison to the thermal curing. Selective UV action is proposed to explain the curing process kinetics.

Dynamic simulation of electromigration in polycrystalline interconnect thin film using combined Monte Carlo algorithm and finite element modeling

Electromigration (EM) is a major failure mechanism in ultralarge-scale integration interconnections. Various atomic migration mechanisms due to the electron wind force, temperature gradients, and thermomechanical stress gradients are involved during an EM failure process. In this study, a methodology that combines a Monte Carlo algorithm and finite element analysis is developed to study the underlying dynamic physical processes of EM, including void nucleation and void growth. The microstructure inhomogeneity of an interconnect thin film and the different atomic diffusivities along various diffusion paths in interconnections are also considered in this three-dimensional dynamic simulation.

Excellent Electrical Characteristics of Praseodymium Oxide Dielectrics on Si Substrate by Reactive RF Sputtering

Praseodymium oxide film was grown on Si substrate by reactive RF-sputtering from a Pr target for TaN metal gate. We found that Pr2O3 gate dielectric with TaN metal gate annealed at 700 o C exhibits a higher capacitance value and lower flatband voltage in C-V curves, and shows the leakage value of ~5x10-7 A/cm2 at a bias of 2 V. This Pr2O3 gate dielectric appears to be very promising for future ultra-large scale integration devices.

A surface adsorption model for electroless cobalt alloy thin films

Thin cobalt alloy films have been obtained using electroless deposition solution with two reducing agents: dimethylamine borane (DMAB) and sodium hypophosphite. This system allows spontaneous and self-activated deposition of barrier layers on Cu lines and via contacts for ultra large scale integration (ULSI) interconnects applications. This work presents a study of the solution composition effects on the material properties and composition of the films. First, we present the deposition rates, the electrical resistance, the various element profiles in the thin film, and the thin film roughness. Next, we discuss the film’s composition and its dependence on the ratio between the reducing agents composition in the solution. The experimental results suggest that the film phosphorous and boron composition is determined by the surface adsorption rates of the reducing agents. Therefore, a surface co-adsorption model of the two reducing agents is proposed, formulated, analyzed, and compared to the experimental results. Finally, we discuss the model and its significance to the formation of high-quality ultra-thin barrier layers.

Deterministic plasma-aided synthesis of high-quality nanoislanded nc-SiC films

Despite major advances in the fabrication and characterization of SiC and related materials, there has been no convincing evidence of the synthesis of nanodevice-quality nanoislanded SiC films at low, ultralarge scale integration technology–compatible process temperatures. The authors report on a low-temperature (400°C) plasma-assisted rf magnetron sputtering deposition of high-quality nanocrystalline SiC films made of uniform-size nanoislands that almost completely cover the Si(100) surface. These nanoislands are chemically pure, highly stoichiometric, have a typical size of 20–35nm, and contain small (∼5nm) nanocrystalline inclusions. The properties of nanocrystalline SiC films can be effectively controlled by the plasma parameters.

Effect of Annealing Ambient on the Self-Formation Mechanism of Diffusion Barrier Layers Used in Cu(Ti) Interconnects

Copper (titanium) [Cu(Ti)] films with low titanium (Ti) concentration were found to form thin Ti-rich barrier layers at the film/substrate interfaces after annealing, which is referred to as self-formation of the barrier layers. This Cu(Ti) alloy was one of the best candidates for interconnect materials used in next-generation ultra-large-scale integrated (ULSI) devices that require both very thin barrier layers and low-resistance interconnects. In the present paper, in order to investigate the influences of annealing ambient on resistivity and microstructure of the Cu alloys, the Cu(7.3at.%Ti) films were prepared on the SiO2 substrates and annealed at 500°C in ultra-high vacuum (UHV) or argon (Ar) with a small amount of impurity oxygen. After annealing the film at 500°C in UHV, the resistivity was not reduced below 16 μΩ-cm. Intermetallic compounds of Cu4Ti were observed to form in the films and believed to cause the high resistivity. However, after subsequently annealing in Ar, these compounds were found to decompose to form surface TiO x and interfacial barrier layers, and the resistivity was reduced to 3.0 μΩ-cm. The present experiment suggested that oxygen reactive to titanium during annealing played an important role for both self-formation of the interfacial barrier layers and reduction of the interconnect resistivity.

Effects of Substrate Materials on Self-Formation of Ti-Rich Interface Layers in Cu(Ti) Alloy Films

In our previous studies, thin Ti-rich layers were found to uniformly cover SiO2/Si substrate surfaces at the interface with Cu(Ti) alloy films after annealing at elevated temperature. These Ti-rich layers were also found to prevent intermixing between the Cu(Ti) alloy films and the substrate, resulting in a simple barrier formation technique, called “self-formation of the diffusion barrier,” which is attractive for fabrication of ultra-large scale integrated (ULSI) interconnect structures. In the present study, to understand the mechanism of self-formation of the Ti-rich barrier layers on the substrate surface, the effects of SiO2/Si, SiN/SiO2/Si and NaCl substrate materials on the interfacial microstructure were investigated. The microstructures were analyzed by transmission electron microscopy (TEM) and secondary ion mass spectrometry (SIMS), and correlated with the electrical properties of the Cu(Ti) interconnects. It was concluded that the chemical reaction of Ti with the substrate materials was essential for the self-formation of the Ti-rich layers.

New formation process of plating thin films on several substrates by means of self-assembled monolayer (SAM) process

This review describes our recent works on the preparation of Ni-alloy films deposited by electroless deposition as a diffusion barrier layer for ultra large-scale integration (ULSI) interconnects by using an all-wet process. In this process, we create a novel wet fabrication process including a self-assembled monolayer (SAM) as an attachment technique between diffusion barrier layer and a substrate. Our proposal process was applied to the substrates of SiO 2/Si and both organic (methyl silsesquioxane) and inorganic (hydrogen silsesquioxane) low- k dielectrics. The key technique of this proposed process is using SAM as a catalyst trapping layer. The Ni-alloy films such as NiB were deposited on catalyzed SiO 2 or low- k substrates. The electrolessly deposited NiB films were found to exhibit sufficient thermal stability and an acceptable barrier property for preventing Cu diffusion into the SiO 2 and low- k dielectrics.

Feasibility Study of 45-nm-Node Scaled-Down Cu Interconnects With Molecular-Pore-Stacking (MPS) SiOCH Films

A feasibility study was done for 45-nm-node Cu interconnects using a novel molecular-pore-stacking (MPS) SiOCH film (k = 2.45), taking electron scattering in the scaled-down Cu lines into consideration. The as-deposited MPS SiOCH film, formed by plasma polymerization of a robust six-member-ring (hexagonal) siloxane with large steric-hindered hydrocarbon side chains, has self-organized subnanometer pores. An oxidation-damage-free dual-hard-mask etching process, along with a benzocylobuten liner technique, preserved the low permittivity of the MPS film in the Cu lines, with excellent interline dielectric reliability. The line aspect ratio was also balanced to decrease not only the interconnect parasitic capacitance but also the Cu line resistivity, which is increased by the electron scattering in the narrow lines. By combining the above etching process and the line-aspect control, the feasibility of the MPS SiOCH film was confirmed with outstanding performance and excellent reliability for the 45-nm-node ultralarge scale integrations

Exploratory study on power-efficient silicon nano-wire dynamic NMOSFET/PMESFET logic

The latest techniques in fabricating silicon-based, vertical surrounding gate MOSFETs (SGFET) instigate the pathway towards building the next generation ultra large-scale integration (ULSI). The study shows the design and optimisation of surrounding gate n-channel MOSFETs and p-channel MESFETs used in dynamic differential domino circuits suitable for an area-efficient technology. Three-dimensional device simulations investigate the maximum device transconductance and minimum OFF current of vertical, metal-gated nano-wire NMOSFETs and PMESFETs as a function of wire radius and doping concentration. Two-dimensional process simulations are carried out on the optimum transistor designs, and non-ideal device characteristics are measured. A family of differential dynamic circuits composed of a two-input AND (OR), and two-input XOR gates and a full adder are built to measure worst-case pre-charge and evaluate function delays, power dissipation and layout area.

Effect of triethanolamine on deposition rate of electroless copper plating

The addition of bis(3-sulphopropyl) disulphide in Cu electroless plating results in Cu superfilling. However, the deposition rate of superfilling copper plating is decreased, which hinders its application for filling Cu into via holes of ultralarge scale integrations. In the present study, the effect of triethanolamine (TEA) on the deposition rate of electroless copper plating was investigated. The deposition rates of electroless plated copper both in traditional and superfilling copper plating were accelerated with an addition of TEA, which was attributed to a decrease in reaction activation energy of a dominant reduction reaction. X-ray diffractometry and atomic force microscopy measurements indicated that with an addition of TEA, the peak intensity ratio /(111)//(200) of electroless plated Cu film was increased and the average surface roughness was decreased.

High-performance and damage-free neutral-beam etching processes using negative ions in pulse-time-modulated plasma

For the past 30 years, plasma-etching technology has led efforts to shrink the patterns of ultralarge-scale integrated (ULSI) devices. However, inherent problems with plasma processes, such as charge build-up and UV photon radiation, have limited etching in the future devices. To overcome these and fabricate sub-50nm devices in practice, neutral-beam etchings have been proposed. In this paper, we introduce damage-free etching processes using neutral beam with negative ions in pulse-time-modulated plasmas. These techniques can achieve damage-free etching processes. They are promising candidates for the practical technology that will be required to fabricate future devices.

Accelerated Chip-Level Thermal Analysis Using Multilayer Green's Function

Continual scaling of transistors and interconnects has exacerbated the power and thermal management problems in the design of ultralarge-scale integrated (ULSI) circuits. This paper presents an efficient thermal-analysis method of O(NlgN) complexity, where N is the number of blocks that discretize the heat-source or temperature-observation regions. The method is named LOTAGre and formulated using the Green's function for heat conduction through multiple-layer materials, which account for the structure of ULSI chips and the accompanying heat sinks and mounting accessories. In addition to analyzing the thermal effects of the distributive heat sources, LOTAGre also considers the ambient temperature effects that are generally excluded in conventional Green's function-based thermal-analysis tools in order to avoid the concomitant analytical complexity. By employing the well-known eigen-expansion technique and classical transmission-line theory, fully analytical and explicit formulas are derived in this paper for the multilayer Green's function with the inclusion of the s-domain version, the homogeneous and inhomogeneous solutions to the heat-conduction equation. Then, the discrete cosine transform and its inversion are employed to accelerate the numerical computation of the homogeneous and inhomogeneous solutions. This paper includes extensive experimental results to demonstrate that LOTAGre can be as accurate as FLUENT, a sophisticated computational fluid dynamics tool, while speeding up the simulation run time by two to three orders of magnitude in comparison to FLUENT as well as conventional Green's function-based thermal-analysis methods. This paper also discusses the limitations of using the traditional single-layer thermal model in thermal analysis for approximating a multilayer chip structure

Electroless Diffusion Barrier Process Using SAM on Low-k Dielectrics

A wet process based on electroless deposition is proposed for the formation of a diffusion barrier layer for Cu wiring in ultra-large scale integration (ULSI) technology. The diffusion barrier layer is formed on a low-dielectric constant (low-) inter level film. In this process, a Pd-activated self-assembled monolayer as a seed/adhesion layer was used as a key step to allow electroless deposition on a dielectric film. The effectiveness of this approach was demonstrated by depositing an electroless layer as the diffusion barrier layer. The electrolessly deposited layer showed a uniform surface, a small grain size, and a high adhesion when deposited on various common inter level dielectric materials with low dielectric constant. The electrolessly deposited layer formed on the low- dielectric film by this method showed a high thermal stability of the effectiveness as a barrier to Cu diffusion at temperatures up to for . The electroless process was found to be reproducible and did not affect dielectric properties of the underlying insulator.