Ultra Large Scale Integration Research Articles

Electron backscattered diffraction analysis of copper damascene interconnect for ultralarge-scale integration

This study focuses on the structures and the crystallographic orientations of copper electrodeposits in trench patterns by the electron backscattered diffraction (EBSD) technique. The EBSD measurement was made on the surface of annealed deposits before and after removal of their over-plated layers by chemical mechanical polishing (CMP) and also on the section normal to trench lines. The textures of the annealed deposit with and without the over-plated layer are almost same. The major and minor orientation components in the annealing textures of trench specimens were approximated by {111}〈110〉 and its twin components, {115}〈110〉 and {115}〈141〉, respectively. Here {hkl}〈uvw〉 indicates that {hkl} is the crystallographic planes parallel to the trench base plane and 〈uvw〉 is the crystallographic directions parallel to the trench line direction. By measuring the line-normal sectional EBSD analysis, the copper electrodeposit in a trench plug is figured as a single crystal having a few of twinning, and hence the over-plated layer has almost the same texture as the trench plug. Therefore, the texture of trench plugs can be inferred by that of the over-plated layer.

Microsampling technique for EBSP inspection on the cross-sections of copper trench lines in ULSIs

The crystal microstructure of copper interconnects in ultra large scale integrations (ULSIs), depends on factors such as the trench line width and patterns. Therefore, inner crystal characterisation of the desired trench lines composed of copper is required. Electron backscatter diffraction pattern (EBSP) inspection has become a powerful technique for analysing the crystal characterisation of interconnects. However, EBSP inspection is sensitive to surface conditions such as contamination and strain. In this study, we applied the focused ion beam (FIB) technology, particularly, the microsampling technique to the preparation of samples for EBSP inspection on the cross-sections of the copper trench lines. As a result, we demonstrate that a damaged layer composed of a crystalline substance is formed on the plane of the copper as revealed by the 30 kV Ga(+) FIB milling, but an EBSP signal is detectable. In conclusion, the cross-sectional sample preparation technique employing microsampling is found to be very powerful for analysing the inner crystal characteristics of the desired copper trench lines by EBSP inspection.

Assessment of on-chip wire-length distribution models

Ultralarge-scale integrated (ULSI) chip design data is needed for an assessment of existing on-chip wirelength distribution models. Data extracted from modern chips such as high-performance microprocessors provide information about actual wire length requirements in ULSI chip designs. These requirements are compared with wirelength estimates obtained by evaluating existing models as functions of Rent's parameters that are extracted from the designs. This brief assesses the extent to which existing models estimate wirelength requirements in 100 ASIC-like control logic designs in the 1.3-GHz POWER4 microprocessor. For each design, physical design characteristics and wirelength requirements are measured and compared with model estimates. Lack of agreement between the data and models is observed for most designs, and possible reasons for the lack of agreement are discussed.

Testing and Diagnostics of CMOS Circuits Using Light Emission from Off-State Leakage Current

In recent years, innovative applications based on the detection of emission sources such as the light emission from off-state leakage current (LEOSLC) of CMOS transistors have been developed for testing and diagnosing modern ultralarge-scale integration circuits. In this paper, we show that LEOSLC can be used to effectively debug circuits, localize defects with a quick turn around time, read the logic state of gates, and extract the internal voltage drop of power distribution grids among others.

Progress in material removal mechanisms of surface polishing with ultra precision

Chemical mechanical polishing (CMP) process is commonly regarded as the best method for achieving global planarization in the field of surface finishing with ultra-precision. The development of investigation on material removal mechanisms for different materials used in computer hard disk and ultra-large scale integration fabrication are reviewed here. The mechanisms underlying the interaction between the abrasive particles and polished surfaces during CMP are addressed, and some ways to investigate the polishing mechanisms are presented.

Novel MIS Ge–Si Quantum-Dot Infrared Photodetectors

The metal-insulator-semiconductor (MIS) Ge-Si quantum-dot infrared photodetectors (QDIPs) are successfully demonstrated. Using oxynitride as gate dielectric instead of oxide, the operating temperature reaches 140 and 200 K for 3-10 and 2-3 /spl mu/m detection, respectively. From the photoluminescence spectrum, the quantum-dot structures are responsible for the 2-3 /spl mu/m response with high operation temperature, and the wetting layer structures may be responsible for the 3-10 /spl mu/m response. This novel MIS Ge-Si QDIP can increase the functionality of Si chip such as noncontact temperature sensing and is compatible with ultra-large scale integration technology.

Errata: “Investigation of various copper seed layers for copper electrodeposition applicable to ultralarge-scale integration interconnection” [J. Vac. Sci. Technol. B 21, 33 (2003)

Errata: “Investigation of various copper seed layers for copper electrodeposition applicable to ultralarge-scale integration interconnection” [J. Vac. Sci. Technol. B 21, 33 (2003)

A Novel Photosensitive Porous Low-k Interlayer Dielectric Film

The characteristics of photosensitive porous low-k methylsilsesquioxane (MSQ) were investigated by electron-beam lithography. Photosensitive low-k MSQ makes it possible to realize via and trench patterns for Cu damascene technology without dry etching processes in the ultra large-scale integrated (ULSI) circuit multilevel interconnect integration.

Spline Based Electronic Modelling

Abstract“Without Mathematics almost everything is zilch”, a scientific maxim, is the kernel for this mathematical piece of research. The basic notion is to formulate mathematical models for devices and circuits deployed in state of the art electronic gadgets. The article searches for a tool to perform the aforementioned operation and finally accouters its models with well known mathematical approximation tools called Interpolators. The analysis of these models is carried out using MATLAB and the simulations are obtained for both frequency dependent and independent device characteristics. The scheme could result in some predicted merits when it allies with Very Large Scale and Ultra Large Scale Integration [VLSI,ULSI] techniques employed in the Electronic chip design industry and Artificial Intelligence. The quondam alliance could result in device miniaturization and the latter may result in the design of robots enabled in the control of electronic environments. However, the latter could be an application [for Robots] or an alliance where the principles of neural networks could be applied for the purpose of mathematical modelling. Thus, the article reveals a solution for how mathematics be applied to engineering and science. (© 2004 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Development of TiSiN CVD process using TiCl4/SiH4/NH3 chemistry for ULSI anti-oxidation barrier applications

CVD-TiSiN may be promising material for O2 diffusion-barrier films in ultra-large scale integrated (ULSI) circuit applications, especially for dynamic random-access memory (DRAM) capacitors. We developed a method for introducing Si into TiN, which is a common material used for diffusion-barrier films. TiSiN films were deposited by reacting TiCl4, SiH4, and NH3 in a hot-wall CVD reactor. We measured TiSiN film deposition rates, composition, crystal structure, and resistivity as a function of SiH4 partial pressure. Adding Si to TiN converts the TiN film structure from columnar grains to columnar-free structure films, thereby effectively removing the diffusion paths for O2. The resistivity of TiSiN films was increased by adding SiH4 to the reactant gas. With an increase in SiH4 partial pressure up to PsiH4 = 0.8 Torr, the resistivity gradually increased, but for PsiH4 = 1.2 Torr, the phase present in the film was almost SiN and its resistivity jumped up. TiSiN film rapid thermal annealing was performed to evaluate the anti-oxidation performance at the temperature range from 400 to 600 °C in 100 Torr of O2. For an increase the Si concentration up to 4.4 at.% improved anti-oxidation performance of TiSiN films. Flow modulation chemical vapor deposition (FMCVD) was used to create TiSiN films with low Cl concentration and improved anti-oxidation performance.

Porous extreme low κ (EL κ) dielectrics using a PECVD porogen approach

The introduction of new dielectrics into silicon chip interconnection technology, to improve the electrical performance of ultra large-scale integration (ULSI), is marked by continuous revisions to meet the International Technology Roadmap for Semiconductors (ITRS) projection. Amorphous a-SiOC:H ( κ = 2.9 ) deposited by plasma-enhanced chemical vapor deposition (PECVD) from linear precursors is now in scale up towards production. Using other precursors like cyclic siloxanes, κ value is reduced to 2.5 at least. The main way to reduce the dielectric constant is to introduce porosity into the film. In this work, a two-step porogen approach is followed to perform extreme low (EL) κ ( κ < 2.5 ) deposition. Firstly, a dual-phase thin film is deposited by PECVD using two advanced precursors: decamethylcyclopentasiloxane (D5) to create a a-SiOC:H matrix and a sacrificial organic precursor. Within the matrix, the organic precursor generates organic inclusions. In a second step, the organic phase is removed by a suitable curing to induce porosity. Various types of organic precursors are investigated and thin films are then characterized. Incorporation and removal of organic molecules from a-SiOC:H material are closely studied using infrared spectroscopy. Using cyclohexene oxide as organic precursor (porogen), κ value of the porous dielectric is measured at 2.2. Nitrogen adsorption isotherms measurements prove the cured material porosity. This work clearly demonstrates the ability of achieving an EL κ with a PECVD porogen approach using D5 as matrix precursor and new organic precursors as porogen.

Effect of Slurry Selectivity on Dielectric Erosion and Copper Dishing in Copper Chemical-Mechanical Polishing

A formidable challenge in the present multi-step Cu CMP process, employed in the ultra-large-scale integration (ULSI) technology, is the control of wafer surface non-uniformity caused by dielectric erosion and Cu dishing. A definitive understanding of the causes of material loss and a physical model for non-uniformity in Cu CMP are thus required. This paper examines the effects of slurry selectivity on dielectric erosion and Cu dishing, in both single- and multi-step Cu CMP processes, in terms of several geometrical and physical parameters. Furthermore, optimal slurry selectivities to mitigate dielectric erosion and Cu dishing in both single- and multi-step polishing are suggested.

Creation of highly functional thin films using electrochemical nanotechnology

This overview describes the results of our recent study of the application of electrochemical nanotechnology to the fabrication of magnetic recording materials, interconnects in ultra-large-scale integrated (ULSI) devices, energy storage materials, and on-chip biosensors. It is important to note that electrochemical processes play significant roles in developing and fabrication such sophisticated materials and devices. In the field of magnetic recording, electrodeposition methods for preparing CoNiFe and CoFe soft magnetic thin films with a high saturation magnetic flux density were newly developed, and the significant issues for obtaining those films are highlighted. In the area of ULSI interconnects, we developed a technique using a self-assembled monolayer (SAM) for direct bonding of the interconnect layer to SiO2, and proposed a novel electroless deposition method for fabricating a diffusion barrier layer. In the field of batteries, electrodeposited SnNi alloy was proposed as a future anode material for Li batteries, and electrochemical MEMS processes were shown to be useful for fabricating micro-sized direct methanol fuel cells (DMFCs) as portable batteries for electronics applications. In the area of chemical sensors, we developed a new process for fabricating field effect transistors (FETs) modified with SAMs for on-chip biosensing applications.

Direct CoSi[sub 2] thin-film formation with homogeneous nanograin-size distribution by oxide-mediated silicidation

By annealing at 460°C for 120s followed by 600°C120s, nanocrystalline CoSi2 thin film with an average grain size of 5nm can be directly formed from a Co∕SiOx∕Si multilayer with the SiOx as a mediated layer. It is found that annealing at 460°C for enough time is crucial for generating enough diffusion channels within the SiOx layer. After these channels are created, subsequent annealing at 600°C keeps these channels open and is responsible for rapid grain growth. In other words, by using two-step annealing, nucleation and growth processes can be effectively controlled and, hence, the resulting microstructure. The homogeneous nanograin-size distribution is important for ultralarge-scale integration technology below 90nm to prevent resistance degradation induced by CoSi2 agglomeration.

Reliability challenges for copper interconnects

In the past few years, copper has been widely used as interconnect metallization for advanced ultralarge-scale integration (ULSI) circuits. Due to the unique chemical properties of copper compared to its predecessor, aluminum, different integration processes must be used for circuit fabrication, that is, the damascene versus reactive ion etch (RIE) process. This difference in integration processes introduces a series of reliability concerns for copper interconnects. After a brief comparison of copper and aluminum interconnects, this article discusses the impact of the differences in the material properties and integration process on reliability. Details are provided on two advanced metallization reliability failure mechanisms: electromigration and stress migration. For copper interconnects, the interface between the cap and the copper metal serves as the fast diffusion path. To improve copper interconnect reliability, development efforts have focused on suppressing copper or copper vacancy diffusion along the interface. Two copper interfaces, the copper/cap interface and the copper/liner (or diffusion barrier) interface, are critical for copper reliability. For commonly used liners, such as Ta/TaN, the copper/liner interface is relatively easy to control compared to the copper/cap interface. For dual-damascene copper lines, a copper via is used to connect the lower level to the upper level. Unlike the robust tungsten stud used in aluminum interconnects, the copper via has been identified as a weak link in dual-damascene copper connections; the majority of early reliability failures can be attributed to the copper vias. The three most critical process factors and elements affecting copper interconnect reliability are copper vias and interfaces and the liner coverage. Using a low- k dielectric with a copper interconnect introduces several new challenges to reliability, including dielectric breakdown, temperature cycle, and stability within packages. Extensive knowledge is urgently needed to understand these issues.

Boron-Retarded Gate Dielectric Formed by Dry Oxidation of Thermal Nitride

We have proposed an approach to grow thin oxynitride gate dielectric (equivalent oxide with the capability for preventing boron penetration. In this method, oxynitride is formed by dry oxidation of ultrathin thermal nitride grown in low pressure. The secondary ion mass spectroscopy profile indicates that its nitrogen peak is located at the gate dielectric surface and possesses concentrations as high as Transmission electron spectroscopy analysis shows that this oxynitride has uniform thickness and a very smooth interface with the Si substrate. Surface roughness is also evaluated by atomic force spectroscopy and exhibits acceptable roughness for device operation. The capability to suppress boron penetration is further proven by the flatband voltage shift in C-V measurement. In addition, its practicality for device operation is also characterized by electrical performances for gate dielectric integrity and reliability. Most importantly, this process is not complicated and fully compatible with existent ultralarge scale integration technology. © 2003 The Electrochemical Society. All rights reserved.

Techniques for high-frequency integrated test and measurement

This paper describes techniques for the on-chip measurement of high-frequency and/or high-bandwidth electrical phenomena in ultra large-scale integration environments. The techniques rely on the integration of multiple compact and robust electronic test devices, or cores, at various locations within an integrated circuit. The cores consist primarily of signal generators that approximate the output of a sigma-delta modulator using finite repetitious bit patterns and a small set of highly robust analog components. They are capable of digitizing on-chip signals at gigahertz rates even using low-cost manufacturing processes. Simple communication between the multiple cores enables the migration of many "board-level" type measurements down to the chip level.

SIMS: from research to production control

AbstractIn 1958, when I joined the Philips Research Laboratories, there were a number of technological problems related to the analysis of solids within Philips that needed analytical support. Because the available (bulk) techniques did not give sufficient results, a new technique, later called secondary ion mass spectrometry (SIMS), was launched that involved the bombardment of a solid target with (primary) energetic ions, followed by mass analysis and ion detection of the sputtered (secondary) target ions.The restrictions of the available infrastructure for such an analytical technique were many: there was no PC for data handling, no internet or database for literature search, the photocopying machine was not yet invented, communication with other scientists had to be done by mail (there was no fax, no E‐mail, no mobile phones) and, what was worse, SIMS was not considered to be a useful analytical technique compared with established techniques!In the years that followed there were many advances: The SIMS instrumentation was improved by better ion optics, advanced electronic equipment and was extended from sector type to quadrupole and finally to time‐of‐flight (TOF) mass spectrometers. The methodology of SIMS was developed step by step (parameters such as lateral and depth resolution, detection limit and quantitative analysis were all optimized in turn). The SIMS technique then made its entrance to solve problems in technology development. In the last two decades SIMS has become an indispensable, reliable, quantitative analytical technique for production control in integrated circuit technology and the after‐sales care of integrated circuits. The philosophy of the provision of an analytical service at the Philips Research Laboratory (hereinafter referred to as ‘our laboratory’) is discussed. After the initial period, where every method (SIMS, AES, ESCA, RBS, etc.) was claimed to be ‘the only one’ (the panacea), we learned how to organize analytical service cost efficiently and for the optimum benefit of the ‘customer’. The core analytical techniques were concentrated in one department and the customer would profit from synergy by using several appropriate analytical techniques for the same problem.Today, the latest developments in SIMS instrumentation keep pace with the latest challenges of the ultra‐large‐scale integration (ULSI) roadmap for integrated circuits, which indicates the dimensions of the circuits that are predicted for the years to come. Copyright © 2003 John Wiley &amp; Sons, Ltd.

Boron diffusion in silicon: the anomalies and control by point defect engineering

Abstract The fabrication of ultra large-scale integrated (ULSI) circuits with ever shrinking feature size requires a continued reduction of diffusion lengths of dopants in Si. However, boron implants undergo an “anomalous” diffusion upon annealing, which is detrimental to the ultra-shallow junction formation. Over the last decade, boron transient diffusion has been much better understood. This implantation-induced transient-enhanced diffusion is known to be driven by the large supersaturation of self-interstitial silicon atoms emitted from the extended defects. The form and evolution of implantation-induced defects with respect to implant species, energy, dose, and annealing temperature have been systematically studied. The improved understanding has led to the development of new doping techniques, such as carbon co-implant, multiple step annealing and point defect engineering (PDE) using co-implantation of high-energy ions. In the PDE approach, high-energy ion bombardments inject vacancies near the surface region and create excessive interstitials near the end of projected range deep inside the substrate. Such manipulation of point defects can retard boron diffusion and enhance the activation of boron. The control of boron diffusion could be used to form ultra-shallow junctions for next generation Si device. In this article, we review the history and recent progress in PDE.

Impact of three-dimensional transistor on the pattern area reduction for ULSI

The impact of three-dimensional transistors, double-gate transistor, trench-isolated transistor (TIS) (using sidewall gate)/FinFET, and surrounding gate transistor (SGT) on the pattern area reduction for ultra-large-scale integration (ULSI) has been described. The pattern area of the gate logic, such as NAND or NOR, with the double-gate transistor, TIS/FinFET or SGT can be reduced to 58, 47, 48%, respectively, compared with the conventional planar case using the same feature size, F. The pattern area of the tapered buffer circuit with the double-gate transistor, TIS/FinFET or SGT can be reduced to 58, 20, 48%, respectively. These three-dimensional transistors can be adapted to ULSI such as application specific integrated circuit (ASIC), microprocessor (MPU), dynamic random access memory (DRAM), and embedded DRAM. The smallest pattern area may be realized with TIS/FinFET or SGT of 47-48% for ASIC, with TIS/FinFET of 42% for MPU, with SGT of 65% for DRAM and with TIS/FinFET or SGT for embedded DRAM. For designing the circuit with TIS/FinFET the design of the trench depth (2F for gate logic, 12F for tapered buffer) is the key issue. The design of the cell library for SGT is a task for the future.