Impact of three-dimensional transistor on the pattern area reduction for ULSI

Abstract

The impact of three-dimensional transistors, double-gate transistor, trench-isolated transistor (TIS) (using sidewall gate)/FinFET, and surrounding gate transistor (SGT) on the pattern area reduction for ultra-large-scale integration (ULSI) has been described. The pattern area of the gate logic, such as NAND or NOR, with the double-gate transistor, TIS/FinFET or SGT can be reduced to 58, 47, 48%, respectively, compared with the conventional planar case using the same feature size, F. The pattern area of the tapered buffer circuit with the double-gate transistor, TIS/FinFET or SGT can be reduced to 58, 20, 48%, respectively. These three-dimensional transistors can be adapted to ULSI such as application specific integrated circuit (ASIC), microprocessor (MPU), dynamic random access memory (DRAM), and embedded DRAM. The smallest pattern area may be realized with TIS/FinFET or SGT of 47-48% for ASIC, with TIS/FinFET of 42% for MPU, with SGT of 65% for DRAM and with TIS/FinFET or SGT for embedded DRAM. For designing the circuit with TIS/FinFET the design of the trench depth (2F for gate logic, 12F for tapered buffer) is the key issue. The design of the cell library for SGT is a task for the future.