Ultra Large Scale Integration Research Articles

A Study of Copper Electroplating of the Submicrometer Scale Patterns

The effect of an accelerator on the morphological evolution during copper electrodeposition was investigated with the designed one-directional (1-D) pattern which has a seed layer only at the bottom of the pattern. Field-emission scanning electron microscope images showed that there was no superfilling found in the pattern with 0.2 μm width trench and no reduction in the surface area during electroplating. This indicates that superfilling in a damascene pattern results from the accumulation of the accelerator. It was found that copper damascene electroplating for ultralarge-scale integration is a simple electroplating system that is controlled by the activation overpotential of adhered organic additives, not by the concentration overpotential of copper ions.

Effect of Ru crystal orientation on the adhesion characteristics of Cu for ultra-large scale integration interconnects

Abstract The adhesion of Cu on Ru substrates with different crystal orientations was evaluated. The crystal orientation of sputter deposited Ru could be changed from (1 0 0) to (0 0 1) by annealing at 650 °C for 20 min. The adhesion of Cu was evaluated by the degree of Cu agglomeration on Ru. Cu films on annealed Ru films with the (0 0 1) crystal orientation showed 28% lower RMS values and 50% lower Ru surface coverage than Cu as-deposited on Ru having the (1 0 0) crystal orientation after annealing at 550 °C for 30 min, which suggest that Cu wettability on the Ru(0 0 1) was better than that on the Ru(1 0 0) plane. The low lattice misfit of 4% between Cu(1 1 1) and Ru(0 0 1) may be the reason for this good adhesion property.

LANTHANUM AND NEODYMIUM SUBSTITUTED Bi4Ti3O12 NANOSTRUCTURES THROUGH SELF-ASSEMBLY

ABSTRACT For the sake of fabricating the ultrahigh density ultralarge scale integration (ULSI) memory chips, the ferroelectric nanostructures growth through self-assembly are studied. In this paper, we synthesize the lanthanum and niobium substituted Bi4Ti3O12 nanostructures on Pt/Ti/SiO2/Si substrates. The method we used here was spin coating precursors with a serious of concentration on the substrates and then annealing at 700°C or 750°C in the oxygen atmosphere to get the self-patterning nano particles. Scanning probe microscope (SPM), and x-ray diffraction (XRD) were used to detect the morphology and the crystalline structure of the nano particles. The well-separated Bi3.15Nd0.85Ti3O12 particles have a typical lateral size about 100–150 nm and height about 20–25 nm. XRD reveals pyrochlore phase in the low concentration samples. The lower the precursor's concentration is, the higher the excess of Bi element is needed to form the pure perovskite nanoparticles.

Ultralow-k silicon containing fluorocarbon films prepared by plasma-enhanced chemical vapor deposition

Low dielectric constant materials as interlayer dielectrics (ILDs) offer a way to reduce the RC time delay in high-performance ultra-large-scale integration (ULSI) circuits. Fluorocarbon films containing silicon have been developed for interlayer applications below 50-nm linewidth technology. The preparation of the films was carried out by plasma-enhanced chemical vapor deposition (PECVD) using gas precursors of tetrafluorocarbon as the source of active species and disilane (5 vol.% in helium) as a reducing agent to control the ratio of F/C in the films. The basic properties of the low dielectric constant (low-k) interlayer dielectric films are studied as a function of the fabrication process parameters. The electrical, mechanical, chemical, and thermal properties were evaluated including dielectric constant, surface planarity, hardness, residual stress, chemical bond structure, and shrinkage upon heat treatments. The deposition process conditions were optimized for film thermal stability while maintaining a relative dielectric value as low as 2.0. The average breakdown field strength was 4.74 MV/cm. The optical energy gap was in the range 2.2–2.4 eV. The hardness and residual stress in the optimized processed SiCF films were, respectively, measured to be in the range 1.4–1.78 GPa and in the range 11.6–23.2 MPa of compressive stress.

All-wet fabrication process for ULSI interconnect technologies

“All-wet process” for fabrication of Cu wiring on a silicon chip was proposed as a novel ultra-large scale integration (ULSI) interconnect technology for integrated circuits (ICs) applications. Electroless-NiB film was deposited on SiO 2/Si substrate modified by self-assembled-monolayer (SAM) activated with PdCl 2. The NiB film formed by this method has highly uniform, with good adhesion to the substrate and with good diffusion barrier characteristics against Cu diffusion. Cu was electrodeposited directly on the electroless NiB film that acted as a seed layer. This was done without any conventional conductive or adhesive layer that is conventionally formed by physical vapor deposition (PDV). The thermal stability of electroless NiB layer as a barrier preventing copper from diffusing into the SiO 2/Si substrate was evaluated by secondary ion mass spectroscopy (SIMS) and sheet resistance measurement at several annealing temperatures. It was confirmed that the electroless NiB film blocked Cu diffusion and kept the layer integrity under annealing temperatures of up to 400 °C for 30 min. The same process of electroless NiB was used for the capping layer that was also formed by “wet process”, as the electroless NiB film deposited selectively onto a surface of Cu wiring was also applicable to a capping layer. We conclude that the proposed process is very promising for sub-100 nm technologies as it offers a variety of desirable properties: it has good step coverage while showing good barrier and seed layer properties.

Preliminary Study of Polymer Removal in 0.25, 0.3, and 0.5 µm Ruthenium Storage Nodes and 0.11 µm, 10.9:1 High-Aspect-Ratio Trenches by Laser-Induced Etching

The demands for new etching technology are increasing because of new materials, such as, ruthenium (Ru), platinum (Pt), and iridium (Ir), that are now being used, and the strict critical dimension (C/D) controls required in today's ultra large scale integrated (ULSI) circuit technology and dynamic random-access memory (DRAM) fabrication lines. Laser etching technology successfully etched organometallic polymers generated after reactive ion etching and ash processing in 0.25, 0.3, and 0.5 µm Ru storage nodes. In this study, the effects of the incident beam profile on the laser-induced etching of the polymers are investigated. Unevenness of the peak energy in the Gaussian beam profile creates unequal etching and heating effects on the polymer removal depending on the irradiating position of the line beam profile on the sample surface. This article discusses for the first time the preliminary results of laser-induced etching with a KrF laser to remove photoresist (PR) and polymer in 0.11 µm deep contact holes with a high-aspect-ratio 10.9:1 trench hole. How deep can the laser etching technology penetrate and strip the PR at a high aspect ratio (A/R) of 10.9:1 and a 0.11 µm hole size? The penetration depth for the PR removal was approximately 1 µm, which is about a 9.1:1 A/R in a 0.11 µm hole with a 1.2-µm-deep trench. Several promising points are discussed on the basis of laser etching in such a high A/R and small 0.11 µm contact hole. Laser-induced etching technology enabled a very uniform penetration depth without any fluctuations, and it also did not show any attack on the edge of the barrier material TiN.

Effects of Dielectric Roughness on Texture of Both PVD Seed Layers and EP Copper

The ability to control the crystallographic orientation of both the seed layer and the electroplated copper grains is important in obtaining highly reliable Cu interconnects for ultra-large scale integration (ULSI) circuitry. One of the factors controlling film texture is the roughness of the deposition surface. In this paper the effects of dielectric roughness on the crystallographic texture of physical vapor deposited (PVD) copper seed layers and, subsequently, on the texture of electroplated (EP) copper have been investigated. Six relevant interlevel dielectric materials were examined: tetraethyloorthosilicate (TEOS), borophosphosilicate glass (BPSG), silane oxide, silicon nitride, SiLKTM (from the Dow Chemical Corporation), and polysilicon were deposited on 200 mm (001) Si wafers. The RMS surface roughness of these dielectric layers, measured by AFM, ranged from 0.32 nm to 20.51 nm. Texture was analyzed on a dedicated x-ray diffractometer equipped with a two dimensional detector collecting incomplete pole figures with a 1.0 degree resolution in pole figure space. The orientation distribution functions (ODF) were calculated using the arbitrary defined cells method and the volume fractions of major fiber texture components were derived from the ODF. The predominant texture components of the PVD and EP copper were (111) and (511) fiber. It was found that the volume fraction of (111) fiber decreased as the dielectric surface roughness increased. One exception was with the SiLKTM dielectric, which produced significantly weaker texture than other dielectrics with similar surface roughness. The copper films deposited on polysilicon, which possessed the roughest deposition surface of all the dielectric films had a random texture. Finally, a mixture of strong (111) and (511) fiber textures of EP copper was achieved on dielectric underlayers with smoother surfaces. The results demonstrate that the deposition surface roughness plays an important role in establishing the texture in overlying PVD and EP Cu films. The texture of PVD and EP copper may serve as a useful indicator of the underlayer roughness.

Process design of Cu(Sn) alloy deposition for highly reliable ultra large-scale integration interconnects

Cu(Sn) alloys were studied as possible candidates for highly reliable interconnects. For conformational deposition of Cu(Sn) alloy seed layer, the effect of Sn doping and the deposition sequence of Cu(Sn) alloy on Cu wettability were investigated by evaluating the agglomeration behavior of Cu(Sn) seed layers on a TaN barrier. Two different sputter-deposited stacked layers were studied; Cu/Sn/TaN/SiO 2/Si and Sn/Cu/TaN/SiO 2/Si structure. Cu(Sn) alloy layers with 5 at.% Sn were agglomerated more than a pure Cu layer due to the lower melting point of Cu by Sn doping. The agglomeration behavior depended on the deposition sequence; Cu/Sn/TaN/SiO 2/Si structure was agglomerated more than Sn/Cu/TaN/SiO 2/Si structure because Cu atoms on liquid Sn layer can diffuse easily. Consequently, for continuous, thin seed-layer deposition, Sn atoms as an alloy element should be deposited after a continuous Cu layer is formed.

Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects

Nonuniform thermal profiles on the substrate in high-performance ICs can significantly impact the performance of global on-chip interconnects. This paper presents a detailed modeling and analysis of the interconnect performance degradation due to the nonuniform temperature profiles that are encountered along long metal interconnects as a result of existing thermal gradients in the underlying Silicon substrate. A nonuniform temperature-dependent distributed RC interconnect delay model is proposed. The model is applied to a wide variety of interconnect layouts and substrate temperature distributions to quantify the impact of such thermal nonuniformities on signal integrity issues including speed degradation in global interconnect lines and skew fluctuations in clock signal distribution networks. Subsequently, a new thermally dependent zero-skew clock-routing methodology is presented. This study suggests that thermally aware analysis should become an integrated part of the various optimization steps in physical-synthesis flow to improve the performance and integrity of signals in global ultra large scale integration interconnects.

Defects in germanium‐doped Czochralski silicon

AbstractGermanium doping of Czochralski (CZ) silicon has attracted attention in recent years. It is pointed out that germanium doping can result in denser voids with small size, which can be eliminated easily by annealing at high temperature, and may improve the gate oxide integrity (GOI) of semiconductor devices. Meanwhile, oxygen precipitation in CZ silicon can be enhanced by germanium, so that the internal gettering (IG) ability of wafers is improved. In addition, it is reported that germanium can suppress the formation of thermal donors (TDs). Thus, it is believed that the germanium‐doped CZ (GCZ) silicon can be used as the substrate of ultra‐large scale integrated (ULSI) circuits, which have the high quality subsurface layer, the high IG ability, and the stable electrical property. (© 2005 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Atomic transport and chemical stability of nitrogen in ultrathin HfSiON gate dielectrics

HfSiO and HfSiON films with thicknesses compatible with the requirements for gate dielectrics alternatives to SiO2 in ultra-large scale integration silicon-based CMOSFET devices were deposited on an ultrathin HfSiO15N interfacial layer on Si(001). These structures were submitted to thermal processing routines typical of post-deposition annealing and dopant activation steps in fabrication technology, namely at 450 or 1000 °C, respectively, and in atmospheres of N2 and/or O2. N transport and loss were determined by nuclear reaction analysis, including sub-nanometric depth resolution profiling with narrow nuclear reaction resonances. The chemical states of N were accessed by angle-resolved X-ray photoelectron spectroscopy. After annealing at 450 °C, N is seen to be mobile, whereas the chemical environment of N is not changed at this temperature. Annealing at 1000 °C renders N mobile and its most abundant chemical state in near-surface regions is unstable. Annealing in O2 atmosphere promotes incorporation of O from the gas phase into the films, partly in exchange for N and O atoms and partly by net incorporation of oxygen in the films. The profiles of the newly incorporated O atoms are also determined with sub-nanometric depth resolution by narrow nuclear reaction resonance profiling.

Electroless Deposited Cobalt-Tungsten-Boron Capping Barrier Metal on Damascene Copper Interconnection

The metal capping barrier deposited by the electroless cobalt tungsten boron (CoWB) alloy plating method for ultralarge scale integration applications was investigated. The CoWB film was formed directly on copper without a palladium catalyst, using dimethyl amin borane (DMAB) as a reducing agent, and it was deposited selectively on 0.25 μm wide copper interconnects separated with 0.25 μm spacing The CoWB thin films were effective barriers against copper diffusion even at CoWB thicknesses as low as 50 nm. Compared with the CoWB film, cobalt tungsten phosphorus films deposited directly on copper using DMAB as a deposition initiator was not effective as a copper diffusion barrier. The plating films contained mainly cobalt with a significant amount of tungsten (up to 20 atom %) and a small amount of boron. Additionally, we propose a newly developed alkaline metal free electroless CoWB plating solution using tetramethyl ammonium hydroxide as a pH adjuster. © 2005 The Electrochemical Society. All rights reserved.

The Grain Size and Microstructure of Jet-Electroplated Damascene Copper Films

Electroplated damascene copper is rapidly replacing aluminum-copper alloys for on-chip interconnect metallization in advanced ultralarge scale integrated (ULSI) semiconductor devices. In addition to a high degree of (111) crystallographic texture, large defect-free grains are desired to enhance the performance and reliability of copper interconnects in such devices. The brightening additive level and dc current density of electroplating baths are two parameters that affect the process gap-filling capability and the degree of additive incorporation in these copper films. Additive incorporation can inhibit grain growth during the room-temperature recrystallization process and therefore affect the final grain size in electroplated copper films. This investigation explores the grain size and microstructure of dc jet-electroplated damascene copper films deposited as a function of current density and brightening additive level after first receiving a high-temperature annealing treatment. In 1.3 μm thick blanket films it was found that large, lognormally distributed, low-resistivity, highly twinned grains with an average diameter of 1.7-1.9 μm could consistently be produced over a wide variety of electroplating conditions. These results suggest that any grain growth inhibition factors, such as remnant electroplating impurities incorporated in the blanket film microstructure after the self-annealing process, can be effectively removed from these films with a sufficient thermal budget to create a stable grain size and microstructure. © 2005 The Electrochemical Society. All rights reserved.

Nanoscale Patterning of Organic and Metallic Features on Semiconductors via Self-Assembly of Soft Materials

Nanostructured materials continue to be the focus of intense research due to their promise of innumerable practical applications as well as advancing the fundamental understanding of these intriguing materials. In particular, the need for metallic and organic features of increasingly smaller size regimes has imposed stringent demands upon chemists to produce a variety of highly functional materials with reduced dimensions. The successful realization of arrayed nanosensor and nanoelectrode production, molecular electronics, ultra large scale integration (ULSI) device fabrication, and nanoelectromechanical systems (NEMS) will require unparalleled precision and control of geometry, aspect ratio, surface morphology, deposition rate, and substrate adhesion without sacrificing throughput or cost effectiveness. While much effort has been expended towards the synthesis of nanoscale structures, one of the most challenging aspects for the nanoscale materials community is the question of how to ‘wire in’ these functional elements with the real world. In this talk, we will describe recent work towards the interfacing of nanoscale patterns of organic molecular and metallic structures with semiconductor surfaces such as silicon, germanium, gallium arsenide and indium phosphide. We have developed a repertoire of chemical reactivities on semiconductor interfaces, and are now patterning them through straightforward and efficient, highly parallel patterning strategies via self-assembly of soft polymer materials. The self-assembled materials direct transport of reagents to the semiconductor so that the reaction takes place in a spatially defined manner, with precise control over the quantity of reagent delivered. Even mixtures of reagents can be ‘sorted out’ by these interfaces to produce nanoscale (∼10 nm) domains of different chemical functionalities, simultaneously. We will describe these and related approaches towards precise patterning of semiconductor surfaces, entirely via wet-chemical processes that are compatible with existing fabrication strategies.

Grain Growth Mechanism of Cu Thin Films

Since Cu was found to be attractive as interconnect materials for ultra-large scale integrated (ULSI) Si devices, the electrical properties of Cu films have been extensively studied to prepare low resistance films. It was found in our previous papers that reduction of the electrical resistance of the Cu films was achieved by increasing grain sizes of the Cu films and large-grained Cu films were essential for the low resistance Cu interconnects. The primary factor to increase the grain sizes was also found to be intrinsic and/or extrinsic strain (or stress) introduced into the films. The present paper addresses the driving force of the grain growth of the Cu thin films based on the strain energy criterion model.

Light from Si via dislocation loops

We give a brief overview of the development and recent progress of a new technology, silicon dislocation-engineered light-emitting diodes (LEDs). The dislocation-engineering method enables the development of light emitters in conventional silicon technology. Key and probably unique to this approach is its genuine and total compatibility with the standard ultra-large-scale integration (ULSI) process used to produce complex computer chips.

Interpretation of rent's rule for ultralarge-scale integrated circuit designs, with an application to wirelength distribution models

Computer hardware components have changed significantly since the 1960s, 1970s, 1980s, and even since the early 1990s. Work concerning Rent's memos prior to the present paper has been based on a 1971 interpretation of two unpublished memoranda written in 1960 by E. F. Rent while working at IBM, even though today's computer components are significantly different from those in 1960 and 1971. However, because of the significant changes in the design and implementation of computer hardware components since 1960 and 1971, a new interpretation of Rent's memos is needed for today's components. We have obtained copies of Rent's two memos. In these memos, Rent describes the method that he used to obtain an empirical relationship between properties of the computer hardware components of the IBM 1401 and the IBM 1410 computers. We have studied these memos carefully in order to understand Rent's original intent. Based on our careful reading of these two memos, the personal knowledge of one of us with the 1401 and 1410 computers, and our experience designing ultralarge-scale integrated (ULSI) circuits for high-performance microprocessors, we have derived an historically equivalent interpretation of Rent's memos suitable for today's computer components. The purpose of this paper is to present a new interpretation of the memos and to present an application to wirelength distributions of real ULSI circuitry. In this paper, we will: 1) describe the contents of the memos and Rent's method; 2) provide an historically-equivalent interpretation of Rent's memos for today's computer components; and 3) apply this new interpretation to real ULSI control logic circuitry in the 1.3-GHz IBM POWER4 microprocessor. In this paper, we will show that this new interpretation of the two memos provides improved wirelength distribution models with better qualitative agreement with measurements and more accurate estimates of wirelength distributions and wirelength requirements for real ULSI designs compared with prior methods.

<tex>$hbox HfO_2$</tex>MIS Capacitor with Copper Gate Electrode

Metal-insulator-semiconductor capacitors were fabricated using atomic vapor deposition HfO/sub 2/ dielectric with sputtered copper (Cu) and aluminum (Al) gate electrodes. The counterparts with SiO/sub 2/ dielectric were also fabricated for comparison. Bias-temperature stress and charge-to-breakdown (Q/sub BD/) test were conducted to examine the stability and reliability of these capacitors. In contrast with the high Cu drift rate in an SiO/sub 2/ dielectric, Cu in contact with HfO/sub 2/ seems to be very stable. The HfO/sub 2/ capacitors with a Cu-gate also depict higher capacitance without showing any reliability degradation, compared to the Al-gate counterparts. These results indicate that HfO/sub 2/ with its considerably high density of 9.68 g/cm/sup 3/ is acting as a good barrier to Cu diffusion, and it thus appears feasible to integrate Cu metal with the post-gate-dielectric ultralarge-scale integration manufacturing processes.

Error mechanisms and rates in tunable-barrier single-electron turnstiles and charge-coupled devices

Si -based single-electron tunneling (SET) devices have of late become an important alternative to the metal-based ones, both for ultralarge scale integration (ULSI) electronics and for electrical metrology. We have very recently been designing, fabricating, and measuring SET turnstiles, pumps, and charge-coupled devices using tunable barriers in silicon. Having shown the potential of these devices, we wish to understand the error mechanisms which may manifest themselves, and to predict the level of these errors, in order to decide how feasible these devices will be. In this paper, we devote a substantial amount of analysis to the consideration of the “dynamical” error mechanism. This particular error considers how electrons split up as the barrier is raised, or alternatively how the Coulomb blockade is formed. We then consider a wide variety of other errors, including thermal, frequency, leakage, and heating errors. We show the dependence of the error rate on each of those mechanisms, and predict maxima or minima for the corresponding parameters. In the conclusion, we discuss the various advantages Si-based turnstiles or pumps would offer with respect to the metal-based ones.

Chemically enhanced physical vapor deposition of tantalum nitride-based films for ultra-large-scale integrated devices

Physical vapor deposition (PVD) using ionized metal plasmas (ionized PVD or IPVD) is widely used to deposit conducting diffusion barriers and liners such as Ta and TaN for use in ultra-large-scale integrated (ULSI) interconnect stacks. Ionized PVD films exhibit the low resistivity, high density, and good adhesion to underlying dielectric desired for this application. On the other hand, extending PVD beyond the 45 nm technology node is problematic since IPVD may not provide sufficient step coverage to reliably coat features having high aspect ratio and sub-100 nm dimensions. Alternatively, chemical vapor deposition (CVD) and atomic layer deposition (ALD) can be used to deposit highly conformal metal films, but the electrical performance and interfacial quality may not equal that of PVD. To address future ULSI barrier∕liner deposition needs, a method providing PVD-like film quality and CVD-like step coverage would be highly attractive. We have recently reported a hybrid approach to film deposition, referred to as chemically enhanced physical vapor deposition (CEPVD), in which a chemical precursor is introduced at the substrate during IPVD to provide a CVD component to the overall deposition process. The isotropic precursor flux is intended to provide film deposition on surfaces that are not impacted by the directional ions, such as the lower sidewall of a narrow via or trench. Conversely, the kinetic energy delivered to the surface by the flux of ionized metal may serve to enhance the desorption of CVD byproducts, reduce incorporation of impurities, and increase film density. In order to investigate the potential of CEPVD to deposit barrier∕liner films, we have focused on the Ta-N material system since Ta∕TaN is widely used as a diffusion barrier in Cu damascene processing. IPVD TaN films were deposited by reactive sputtering of a Ta target in Ar∕N2 using a planar magnetron and internal rf coils to provide a secondary ionization plasma for the sputtered neutrals. CEPVD was carried out by introducing a Ta-containing, organometallic precursor [tert-butylimino tris(diethylamino) tantalum] in the vicinity of the substrate surface during IPVD. Film thickness and step coverage were determined by cross-sectional scanning electron microscopy (SEM). Film composition, chemical state, and crystal structure were characterized using Auger electron spectroscopy, x-ray photoelectron spectroscopy, and x-ray diffraction, respectively. Resistivity was measured by four-point probe. Cross-sectional SEM showed improved step coverage over IPVD TaN. CEPVD film properties were highly process dependent; however, unlike IPVD TaNx films that vary in stoichiometry but not purity, CEPVD “TaN” films contained relatively large amounts of carbon (∼30%–60%) and could best be described as TaCxNy. Resistivity as low as ∼370μΩcm was obtained for planar films of approximately 90 nm in thickness.