Ultra-deep Submicron Research Articles

Physical Design Implementation to Enhance Performance of Ultra-Deep Sub-micron (UDSM) Hard Macro-based Design

Physical Design Implementation to Enhance Performance of Ultra-Deep Sub-micron (UDSM) Hard Macro-based Design

INDIDO: A novel low-power approach for domino logic circuits

Power dissipation in Nanoelectronic circuits at advanced technology nodes is dominated by leakage power dissipation. This is due to an increase in short channel effects in the scaled transistors.The VLSI industry is seeking alternative options to enhance the performance of portable electronic systems by ensuring higher speed and reduced power dissipation. In the ultra-deep submicron (DSM) regime, a new device called the fin-shaped field effect transistor (FinFET) was developed to replace CMOS technology. FinFET, a multi-gate device, significantly reduces power dissipation compared to planer MOS (Metal Oxide Semiconductor ) transistor, but it doesn’t entirely resolve the issue. To further reduce power dissipation in the ultra DSM regime, low power approaches are required. Domino logic, a widely-used dynamic logic, is commonly utilized in high-speed VLSI architectures. In this research work, a novel INput Dependent Inverter DOmino (INDIDO) logic approach for low-power domino logic circuits using FinFET devices is proposed. A comparative analysis between the proposed INDIDO method and the existing approaches is performed for domino logic circuits for various performance metrics at the 16 nm technology node. In this research, various circuits like domino buffer, domino OR, domino AND, domino XOR and domino half adder are designed using the proposed INDIDO approach.The proposed INDIDO FinFET buffer circuit offers significant improvement in energy efficiency and FOM (Figure of Merit) by 53.18% and 82% respectively as compared to conventional FinFET footed domino buffer circuit. Beside this, proposed circuits like INDIDO OR, INDIDO AND, INDIDO XOR and INDIDO Half adder circuit follow the same trend as INDIDO buffer circuit and show better performance parametres in comparison to the existing low power domino approaches as well. In addition to this, the proposed INDIDO buffer circuits are also analyzed for PVT(process voltage and temperature) variability.This whole analysis makes us to conclude that proposed INDIDO approach reduces power dissipation and delay penalty, have high noise tolerance capacity, more immunity against PVT variations and high energy efficiency in comparison to the already existing techniques.

Ultra-optimized demultiplexer unit design in quantum-dot cellular automata nanotechnology

Integrated circuit designers face challenges in using complementary metal oxide semiconductor (CMOS) technology as it has a large leakage current and scalability challenge in ultra-nanoscale regime. Quantum-dot Cellular Automata (QCA) is a nanotechnology that can replace CMOS for designing ultra-deep submicron circuits and overcoming CMOS limitations. In this research paper, a novel area-efficient 1:2 demultiplexer is proposed using QCA technology. A demultiplexer is an important combinational circuit used in communication systems and computer memories. It receives serial input data and routes data in parallel to multiple outputs. QCA Designer and QCA Pro-tools are used for layout, simulation, and analysis of power dissipation. 11 QCA cells are utilized in the construction of the proposed 1:2 demultiplexer. The cell area and layout cost of the proposed demultiplexer have improved to 42.11 % and 55.56 % of the current best design, respectively. An essential factor to consider when developing integrated circuits is power dissipation. The proposed design dissipates less power. The energy dissipation of the proposed design has improved to 57.67 % at the kink energy level of 1.5 of the current best design.

Parity Generators for Nanocommunication Systems Using QCA Nanotechnology

Quantum-dot cellular automata (QCA) nanotechnology has the capability to design highly-dense, ultra-low power, and high-speed digital circuits at ultra-deep sub-micron (ultra-DSM) level. QCA nanostructure provides a transistor-free operation that saves large energy dissipation as compared to the conventional metal oxide semiconductor field effect transistor (MOSFET) technology. In this paper, 3-input exclusive-OR (XOR) and exclusive-NOR (XNOR) gates are presented using QCA cells. XOR and XNOR (XOR-XNOR) gates are further utilized to design the 2-, 3-, 4-, and 5-bit even and odd parity generators. The QCA-based 3-input XNOR gate is constructed using only 10 QCA cells and two clock phases. The target of the presented designs is to use the minimum count of QCA cells in a simplistic way to form the higher bit-size parity generators. The comparative analyses for the different performance metrics are showing that the developed designs are performing well for the cell count, latency, area, and layout cost as compared to the existing designs. Energy dissipation for the designs is calculated to check the energy efficiency by using the QCA Designer-E and QCA Pro tools.

Design and Optimization of Ultradeep Submicron CMOS Inverter Using a Unified All Regional MOSFET Model

Complementary Metal Oxide Semiconductor (CMOS) has always remained the dominant integrated circuit technology specifically for designing digital circuits. This paper examines the modelling (utilizing $\alpha$-power based MOSFET model), simulation (utilizing HSPICE simulation) and optimization (utilizing Particle Swarm Optimization (PSO) and Artificial Bee Colony (ABC) techniques) of ultradeep submicron CMOS based digital inverter, performs insightful analysis and extracts formulas for the optimal transistor sizing. Additionally, the study serves as an implementation forum for the thermal analysis of transient characteristics of CMOS inverters at the ultradeep submicron technology node (at 300K and 400K). The results lie within the acceptable range of 1-10\%.

An efficient low power method for FinFET domino OR logic circuit

Advancement in the metal oxide semiconductor field effect transistor (MOSFET) technology leads to large power dissipation, and propagation delay due to extreme scaling of the transistor. So, very large-scale integration (VLSI) industry requires alternative options to meet the demands of the customers. Fin-shaped field effect transistor (FinFET) is new innovative device to replace the MOSFET technology in ultra-deep submicron (ultra-DSM) regime. FinFET mitigates power dissipation to the large extent as compared to the MOSFET, but still the impact of power dissipation degrades the circuit performance. Leakage reduction techniques are further needed in ultra-DSM regime to reduce the power dissipation. Domino logic is commonly used in large memories, and high-speed processors. In this article, a low power domino logic is proposed using FinFET devices. The proposed method is compared to the existing similar domino logic approaches for the different performance metrics at 7 nm technology node using Cadence's tools. The proposed method effectively reduces the leakage power dissipation, and delay penalty for the different logic circuits. The reliability of the domino OR logic is checked by estimating the temperature, and multiple parallel fins variations. The proposed method has a high noise tolerance capacity in term of unity noise gain (UNG) for the domino OR logic as compared to the existing approaches.

Single layer adder/subtractor using QCA nanotechnology for nanocomputing operations

Quantum-dot cellular automata (QCA) nanotechnology is a suitable replacement for the widely accepted complementary metal oxide semiconductor (CMOS) technology. CMOS technology faces the issues of high-leakage current and non-scalability in the ultra-deep submicron (ultra-DSM) regime. It motivates the researchers to explore new technologies for further advancement of the field. QCA nanotechnology is energy-efficient technology and it overcomes the issues of CMOS technology in ultra-DSM regime. In this paper, a novel 3-input XOR structure is presented using QCA nanotechnology. The full adder and the full subtractor circuits based on the 3-input XOR gate are developed. A circuit for the full adder/subtractor nanostructure is proposed in the paper. All the proposed designs are optimal, fault-tolerant and single-layered. The proposed full adder contains only 21 QCA cells, while 22 QCA cells are required for the proposed full subtractor. The proposed full adder/subtractor structure consists of only 30 QCA cells. The proposed designs are compared with the existing designs for the number of QCA cells, total cell area, total covered area, area utilization, clock latency, QCA layout cost, and crossover requirement. The energy-efficient behaviour of the proposed circuits is calculated using the QCA Designer-E and the QCA Pro tools.

ANFIS Based Thermal Estimation of Ultradeep Submicron Digital Circuit Design

In this paper, the use of the Adaptive Neuro Fuzzy Inference System (ANFIS) to model the CMOS inverter is discussed as a tool for developing and simulating CMOS logic circuits at the ultradeep submicron technology node of 22nm. The ANFIS structures are built and trained using MATLAB software. The ANFIS network was trained using data obtained from the analytical model (at 298.15K and 398.15K). For training, two methodologies are used: a hybrid learning method based on back-propagation and least-squares estimation, and back-propagation. The effect of the ANFIS model's structure on the accuracy and performance of the CMOS inverter has also been investigated. Further, simulation through HSPICE using (Predictive Technology Model) PTM nominal parameters has been done to compare with ANFIS (trained using an analytical model) results. The comparison of ANFIS and HSPICE suggests the ANFIS modelling procedure's practicality and correctness. The findings demonstrate that the ANFIS simulation is significantly faster and more comparable than the HSPICE simulation and that it can be easily integrated into software tools for designing and simulating complicated CMOS logic circuits.

CNTFET Circuit-Based Wide Fan-In Domino Logic for Low Power Applications

Carbon nanotube field effect transistors (CNTFETs) are the best alternative option for the metal oxide semiconductor field effect transistor (MOSFET) in the ultra-deep submicron (ultra-DSM) regime. CNTFET has numerous benefits such as lower off-state current, high current density, low bias potential and better transport property as compared to MOSFET. A rolled graphene sheet-based cylindrical tube is constructed in the channel region of the CNTFET structure. In this paper, an improved domino logic (IDL) configuration is proposed for domino logic circuits to improve the different performance metrics. An extensive comparative simulation analysis is provided for the different performance metrics for different circuits to verify the novelty of the proposed IDL approach. The IDL approach saves the leakage power dissipation by 95.61% and enhances the speed by 87.10% for the 4-bit full adder circuit as compared to the best reported available domino method. The effects of the number of carbon nanotubes (CNTs), temperature, and power supply voltage variations are estimated for leakage power dissipation for the 16-input OR (OR16) gate. The reliability of different performance metrics for different circuit is calculated in terms of uncertainty by running the Monte Carlo simulations for 500 samples. Stanford University’s 32[Formula: see text]nm CNTFET model is applied for circuit simulations.

Design and Simulation for NBTI Aware Logic Gates

Reliability of the electronic circuits is one of the most prominent factor in the development of very large-scale integration (VLSI) industry. Huge demand for compact size and high performance of electronic devices leads the excessive scaling of the transistor. Aggressive scaling of transistor in ultra-deep submicron regime arises the problem of short channel effects (SCEs) which is the major reason for subthreshold leakage and reliability issues. Negative input voltage to p-channel metal oxide semiconductor (PMOS) transistor causes interface traps at silicon dioxide and silicon substrate interface which leads to increase in the threshold voltage of the transistor and degrades the circuit performance. The design parameters exceed the design specification and causes the variations in timing due to negative bias temperature instability (NBTI) degradation that results logic failure. This paper presents the impact of reliability variations on 32 nm complementary metal oxide semiconductor (CMOS) predictive technology model (PTM) and 20 nm multi-gate PTM fin-shaped field effect transistor (FinFET) circuits. NBTI degradation of various circuits are evaluated with the help of Cadence’s virtuoso tool containing Spectre native reliability simulator. Simulation results are showing that NBTI degradation causes variations in threshold voltage and alters the output performance.

An Analytical Study Of Temperature Dependence of Scaled CMOS Digital Circuits Using α-Power MOSFET Model

Aggressive technological scaling continues to drive ultra-large-scale-integrated chips to higher clock speed. This causes large power consumption leading to considerable thermal generation and on-chip temperature gradient. Though much of the research has been focused on low power design, thermal issues still persist and need attention for enhanced integrated circuit reliability. The present paper outlines a methodology for a first hand estimating effect of temperature on basic CMOS building blocks at ultra deep submicron technology nodes utilizing modified α-power law based MOSFET model. The generalized α-power model is further applied for calculating Zero Temperature Coefficient (ZTC) point that provides temperature-independent operation of high performance and low power digital circuits without the use of conditioning circuits. The performance of basic digital circuits such as Inverter, NAND, NOR and XOR gate has been analyzed and results are compared with BSIM4 with respect to temperature up to 32nm technology node. The error lies within an acceptable range of 5-10%.

Modeling of TID-induced leakage current in ultra-deep submicron SOI NMOSFETs

In order to study the total ionizing dose effects (TID)-induced degradation mechanism of 130 ​nm partially depleted (PD) silicon-on-insulator (SOI) NMOSFETs, a SPICE model including the TID effects was established with Verilog-A.The total ionizing dose effects will lead to the threshold-voltage shift and the leakage current increase of SOI NMOSFETs. The increase of leakage current in the STI region is the main factor leading to degradation of characteristics of devices, which will form a parasitic transistor. Based on the standard BSIM SOI process model, the SPICE model of leakage current of the STI parasitic transistor is added, and the variation of equivalent gate width and gate oxide thickness caused by radiation-induced trapped charges are considered.The devices with different width-length-ratios and different bias conditions are considered in our experiments, and the model can effectively reflect the variation of current characteristics before and after radiation, and provide a reference to develop a radiation-hardening technology.

Noise Immune Pseudo-Stacked-wide keeper Domino technique for Ultra Deep Submicron Technology

The demand of high performance with low leakage has extensively exploited domino logics for high speed computing and microprocessor systems. But this benefit gets compromised with scaling of technology leading to increase in sub-threshold leakage and reduced noise immunity. This paper presents a new performance oriented circuit technique for higher noise immunity with ultra-low leakage and better speed design. The proposed circuit technique employs pseudo buffer along with stacking effect to reduce leakage and power dissipation. The modified keeper transistor in the proposed circuit helps to reduce circuit delay and also improve noise sensitivity. The simulation has been carried out using Cadence spectre 90nm technology with results indicating 57% to 68% less leakage and 77% less power dissipation. The Energy-Delay-Product for the proposed circuit is the lowest in comparison to other existing techniques. The high values of Average Noise Threshold Energy, Unity Noise gain and Energy Normalized Average Noise Threshold Energy proves the improvement in Noise robustness over the previous techniques.

Ultralow power, noise immune stacked‐double stage clocked‐inverter domino technique for ultradeep submicron technology

SummaryHigh‐performance system widely uses domino gates due to their high speed and low power. Everlasting demand of technology scaling increases leakage current in domino gates. These make domino circuit less immune to noise. This paper present a new energy efficient circuit technique for ultralow power consumption and higher noise immunity design for wide fan‐in gates. The proposed circuit techniques reduce leakage from the evaluation network of the domino circuit with help of stacked footer approach involving clocked inverter in double stage domino. This approach has an added advantage of circuit robustness. The proposed circuit exerts less power dissipation and improved unity noise gain compared with a conventional domino circuit. The immunity is demonstrated with the help of average noise threshold energy, energy normalized ANTE (ANTE, ANTE/Energy). The simulation of the circuit is carried out by using 90 nm technology in Cadence TCAD tools.

On the mathematical insight of moderate inversion for ultradeep submicron CMOS technologies

A MOSFET operating in the moderate inversion region is important for low power applications. Though various models are available in the literature expressing the drain current characteristics for weak and strong inversion regions, the model equations for transistors operating in moderate inversion for short channel devices are absent. Moreover, the boundary conditions specifying weak, moderate and strong inversion regions are necessary to have a smooth transition from one region to another. In this paper, an $$\alpha $$ power law based approximate model for strong, moderate and weak inversion region is proposed using mathematical series expansions. The results obtained are verified using industry standard BSIM4 and lies in between error range of 5–10 $$\%$$ .

Adaptive Multi-Voltage Scaling with Utilization Prediction for Energy-Efficient Wireless NoC

Networks-on-Chip (NoCs) are fast becoming the de-facto communication infrastructures in chip multi-processors for large-scale applications. Wireless NoCs (WNoCs) offer a promising solution to reduce the long-distance communication bottlenecks of conventional NoCs by augmenting them with single hop, long-range wireless links. However, power consumption in routers and network elements still remains considerably high at ultra-deep submicron technologies. Analysis of network resources for several benchmarks shows that, utilization is application dependent and the desired performance can be achieved even without operating all resources at maximum specifications. In this work, we propose an energy-efficient WNoC architecture using Adaptive Multi-Voltage Scaling (AMS) to dynamically vary supply voltage for NoC routers and Wireless Interfaces (WIs) without adversely impacting performance. The proposed scheme uses a probabilistic model to predict router utilization during different application phases and scales voltage accordingly. It further reduces network energy by power-gating WIs that are not engaged in active communication to minimize their power consumption. We present detailed utilization estimation procedure, AMS control mechanism, and its hardware implementation. It saves up to 56 percent in network packet energy consumption and 62.50 percent power consumption in WIs for 256 core system as compared to baseline architectures without incurring significant performance penalty and area overheads.

Scalable [formula omitted]-power law based MOSFET model for characterization of ultra deep submicron digital integrated circuit design

Analytical circuit design, optimization, characterization and development of design methodology for digital circuits using nanoscale CMOS devices require compact equations. Such equations need to include first order short channel phenomena relevant to the nanoscale technology nodes being used. The present paper demonstrates that α-power model can be updated to include velocity overshoot necessary to characterize devices at ultradeep submicron technology nodes. Further, the three α-power model parameters (velocity saturation index α, transconductance parameter K1 and threshold voltage Vth) expressing MOSFET drain current has been expressed in terms of predictive technology model (PTM) parameters. Representative basic CMOS cells belonging both to inverter and transmission gate categories have been analytically characterized using the updated α-power model up to ultradeep submicron technology node with BSIM verification. It has been shown that consideration of velocity overshoot is important for accurate prediction below 40nm.

Design of Low Leakage PVT Variations Aware CMOS Bootstrapped Driver Circuit

This paper describes a novel complementary metal oxide semiconductor (CMOS) bootstrapped driver circuit for driving large resistive capacitive (RC) loads. The proposed bootstrapped driver reduces the leakage as well as process, voltage and temperature (PVT) variations from the boosted nodes with higher switching speed. Very large scale integration (VLSI) designers need boosted output for the logic circuits which are operating in ultra-deep submicron regime under widespread use of low voltage. Proposed CMOS bootstrapped driver circuit is easy in design; built with minimum number of transistors and have high boosting efficiency with sharp output performance. Comparative evaluations with existing bootstrapped driver circuits are reported. Simulation results are derived by HSPICE tool with predictive technology model (PTM) bulk CMOS process fabrication at 32 nm technology node. The ability of large leakage reduction makes this driver superior as compared to active drivers. An average of 96.97% leakage current is saved at nominal ultra-low voltage of 0.15 V. Monte-Carlo analysis indicates that the proposed bootstrapped driver has less sensitivity of PVT variations. The power consumption and delay sensitivities are reduced by 10 × and 4.12 × as compared to conventional circuit.

Problems and Properties of a Current Amplifier When Realized in Ultra Deep Sub-micron Technology

Problems and Properties of a Current Amplifier When Realized in Ultra Deep Sub-micron Technology

Reliability Analysis of P+ Pickup on Anti-ESD Performance in Four CMOS Low-Voltage Technology Nodes

ABSTRACTN-channel metal-oxide semiconductor field-effect transistor (MOSFET) devices in I/O ESD protection circuits are often drawn in the parallel multi-finger construction. However, a non-uniform turned-on characteristic always occurs with this type of construction; i.e. the resulting sub-MOSFETs cannot be turned on at the same time. The ESD high-current will thus be conducted through a few turned-on MOSFETs, seriously impacting the ESD reliability and capability. On the source-side, the P+ pickup layout placement influence on an nMOSFET ESD capability of input/output pads for power-management popular 0.6- to 0.18-μm BCD (bipolar–complementary metal oxide semiconductor–diffusion metal oxide semiconductor) CMOS (complementary metal oxide semiconductor) technologies is investigated in this paper. However, the It2 decreasing percentage in an even- and full-adding type of P+ pickup stripe in the source end, as compared with that of a corresponding NonePickup Ref. type, is actually disadvantageous to the ESD immunity. The secondary breakdown current (It2) decreasing percentages have a range of 2.43%–63.31% for the four process nodes. This is very serious for the three technology nodes especially in the ultra-deep submicron 0.18-μm technology. On the contrary, the 0.35-μm technology is a critical process node. Furthermore, the figure of merit (FOM) for a device's ESD performance in a multi-finger type MOSFET can be used to well characterize and predict the device's It2 behaviour using an empirical methodology proposed in this work.