Types Of Wafers Research Articles

Ultrasmall-sized light-emitting diodes fabricated by ion implantation based on GaN epitaxial wafers with fully activated or unactivated p-GaN.

A key challenge in realizing ultrahigh-resolution displays is the efficient preparation of ultrasmall-sized (USS) light-emitting diodes (LEDs). Today, GaN-based LEDs are mainly prepared through dry etching processes. However, it is difficult to achieve efficient and controllable etching of USS LED with high aspect ratios, and LED sidewalls will appear after etching, which will have a negative impact on the device itself. Herein, a method for preparing USS LED based on GaN epitaxial wafers is reported (on two types of wafers, i.e., with p-GaN fully activated and unactivated). F-ions are injected into the intentionally exposed areas on the two types of wafers to achieve device isolation. The area under the micro-/nano-sized protective masks (0.5, 0.8, 1, 3, 5, 7, 9, and 10 µm wide Ni/Au stripes) are the LED lighting areas. The LED on the p-GaN unactivated wafer (UAW) requires further activation. The Ni/Au mask not only serves as the p-electrode of LED but also Ni as a hydrogen (H) removing metal covering the surface of p-GaN UAW that can desorb H from a Mg element in the film at relatively low temperatures, thereby achieving the selective activation of LED lighting areas. Optoelectronic characterization shows that micro-/nano-sized LED arrays with individual-pixel control were successfully fabricated on the two types of wafers. It is expected that the demonstrated method will provide a new way toward realizing ultrahigh-resolution displays. Analyzing the changes in the current flowing through LED (before and after selective activation) on the F-injected p-GaN UAW, it is believed that depositing H removing metal on p-GaN UAW could possibly realize the device array through the selective activation only (i.e., without the need for ion implantation), offering a completely new insight.

Why is gallium-doped silicon (sometimes) stable? Kinetics of light and elevated temperature induced degradation

Light and elevated temperature induced degradation (LeTID) can induce high power losses in photovoltaic modules built from various types of silicon wafers. After the industry's rapid transition from Boron- to Gallium-doping, it is still unclear how the new dopant atom affects the degradation process and why it entails an apparently higher resistance to LeTID. We treat identically processed Gallium-doped Czochralski silicon wafers at 16 different conditions by screening temperature and minority charge carrier density (in the following “injection”). The illumination source is regulated to keep the injection constant at each condition. This method allows for an improved quantitative analysis of the LeTID kinetics based on effective lifetime measurements. Our results show that Gallium-doping shifts the equilibrium between the formation of LeTID defects and their temporary recovery (TR) to the latter, leading to a reduced degradation extent at temperatures up to 80 °C. The efficacy of this TR-induced LeTID suppression depends delicately on both temperature and injection which explains why Gallium-doped silicon appears to be LeTID-immune at high illumination intensities. By accounting for the influence of TR, we extract activation energies and injection exponents that relate to the dominant defect transitions separately, revealing a large discrepancy to effective values reported in literature. The increased accuracy of our kinetic parameters enhances the reliability of existing efficiency models. Finally, we find that a degradation as expected under field conditions can be probed at a 100-fold accelerated rate in the lab. By shining light on LeTID kinetics in Gallium-doped silicon, we explain the dopant atoms' influence on the degradation behavior, establish a basis for precise yield modelling and formulate guidelines for accelerated test protocols.

(Invited) Modified SAB Methods for Hybrid and All-Cu Bonding for 3D Integration below 200ºC

Two methods of Surface Activated Bonding (SAB) will be proposed to enable low-temperature hybrid bonding for 3D integration.A modified one involves surface activation processes using Ar fast-atom-beam bombardment with simultaneous co-sputtering of Si nano-adhesion layer, followed by sequential plasma irradiation with N2 radicals. These processes combine hydrophilic treatment and bonding in a low-vacuum chamber. The Si nano-adhesion layer and the sequential plasma treatment appear to enhance hydrophilicity, which enables low-temperature bonding of both Si oxides and Cu pads as hybrid bonding. Bonding in a low-vacuum environment helps to avoid void generation caused by air entrainment.The other one is the standard SAB. But we will connect two device wafers not in a hybrid bonding but in all-Cu bonding. A small insulation layer surrounds the area around the Cu electrode on the wafers, while the rest is covered with Cu solid layers. These solid layers constitute the ground layer, power layer, or their paired layers and may contribute to heat dissipation when connected to thermal vias. The two wafers are connected only by bonding on the Cu electrodes and solid layers. The insulating parts around the Cu electrodes do not necessarily have to be bonded, and the gaps may be kept in a vacuum. Of course, the bonded surfaces need to be flattened, and a new division and layout design of the solid electrode will be required.Cu-Cu direct bonding is possible at room temperature by applying the standard SAB directly. Of course, this requires bonding in an ultra-high vacuum condition, which inevitably reduces the throughput. However, room temperature bonding is overwhelmingly advantageous for bonding different types of devices and wafers. It is expected to become a powerful tool for 3D heterogeneous integration of devices in the future. Figure 1

Inverted pyramid structures fabricated on monocrystalline silicon surface with a NaOH solution

Low-cost aqueous alkaline etching has been widely adopted for monocrystalline silicon surface texturing in current industrial silicon solar cells. However, conventional alkaline etching can only prepare upright pyramid structures on mono-crystalline silicon surfaces. This study demonstrates for the first time the use of ethylene glycol butyl ether (EGBE) to regulate aqueous anisotropic alkaline etching and prepare inverted pyramid structures on monocrystalline silicon surfaces. Acidic metal-catalyzed etching solutions are not the best choice for monocrystalline silicon due to their inherent disadvantages, such as noble metal pollution and relatively high costs. The one-step method to produce the inverted pyramid structures by using alkaline etch with EGBE additive is simple and inexpensive, does not generate noble metal pollution, and especially compatible with current industrial silicon solar cell production lines. With the use of a sodium hydroxide (NaOH) solution containing a low-cost additive, inverted pyramid structures can be prepared on mono-crystalline silicon surface in a short time. This method is suitable for various types of silicon wafers and has great potential for industrial solar cell applications.

Preparation of thin-film SOI wafer by low-dose ion implantation

Silicon-on-insulator (SOI) devices have many advantages, such as high speed, low energy consumption, radiation-hard, and high integration. In this paper, the separation by implanted oxygen process under low-dose implantation conditions is studied by the two-step implantation method combined with the internal thermal oxidation process. The effects of different types of silicon wafers and different implantation doses on SOI surface defects, top Si thickness, buried oxide (BOX) layer thickness, BOX layer breakdown voltage, and top Si defect density were investigated. Ultra-thin SOI wafers are prepared by epitaxial silicon wafers and control the first implantation dose. The number of surface defects of SOI materials is less than 100 counts, the breakdown voltage of the BOX layer is about 7.8 MV/cm, and the top Si dislocation density is about 8 × 103 cm−2.

Formation of light-emitting defects in silicon by swift heavy ion irradiation and subsequent annealing

High-resistivity floating-zone silicon (FZ-Si) and n-type (4.5 Ohm·cm) Czochralski silicon (CZ-Si) wafers were irradiated at room temperature with 167 MeV Xe ions to fluences ranging from 5·1010 to 5·1011 cm−2. Temperature dependent photoluminescence (PL) measurements were performed to characterize the as-implanted and annealed silicon wafers. It was found that irradiation with swift heavy ions (SHI) leads to the formation of light-emitting defects in both types of silicon wafers. Low-temperature annealing (400 °C) leads to a significant increase of the photoluminescence intensity. In addition, the photoluminescence decreases for increasing measurement temperatures and eventually quenching is observed for temperatures larger than 80 K. The type of silicon wafer (FZ or CZ) does not significantly influence the defect-related light-emitting properties. This implies that low fluence SHI irradiation is a promising method for creation of light-emitting defects in silicon.

Research progress of light and elevated temperature-induced degradation in silicon solar cells: A review

At present, passivated emitter and rear cell (PERC) solar cells dominate the photovoltaic industry. However, light and elevated temperature-induced degradation (LeTID) is an important issue responsible for the reduction of PERC efficiency, which may lead to up to 16% relative performance losses in multicrystalline silicon solar cells, and this degradation occurs in almost all types of silicon wafers. Even in next-generation silicon solar cells like Tunnelling oxide passivated contact (TOPCon) and Heterojunction with Intrinsic Thin-layer (HJT) solar cells, LeTID can still cause an efficiency loss up to 1% relative. LeTID is a long process in terms of time during the whole cycle of degradation and regeneration, which will seriously affect the conversion efficiency and stability of solar modules, and hence increase the cost of electricity generated by solar cells. Furthermore, after years of research on LeTID, researchers are yet to determine the specific cause of LeTID. In this paper, we refer to specific literature, briefly describe the development history of LeTID, introduce the phenomena of LeTID in crystalline silicon solar cells, and describe its characteristics. In addition, we also analyzed the fundamental causes of LeTID, and found that the cause may be related to metal impurities or hydrogen contained in solar cells. At present, in view of the participation of hydrogen in LeTID and other existing related theories, this paper introduces several methods to inhibit LeTID in crystalline silicon. Finally, the content of this paper is summarized, and the development of solar cells in the future is prospected.

Status and perspectives of crystalline silicon photovoltaics in research and industry

Crystalline silicon (c-Si) photovoltaics has long been considered energy intensive and costly. Over the past decades, spectacular improvements along the manufacturing chain have made c-Si a low-cost source of electricity that can no longer be ignored. Over 125 GW of c-Si modules have been installed in 2020, 95% of the overall photovoltaic (PV) market, and over 700 GW has been cumulatively installed. There are some strong indications that c-Si photovoltaics could become the most important world electricity source by 2040–2050. In this Review, we survey the key changes related to materials and industrial processing of silicon PV components. At the wafer level, a strong reduction in polysilicon cost and the general implementation of diamond wire sawing has reduced the cost of monocrystalline wafers. In parallel, the concentration of impurities and electronic defects in the various types of wafers has been reduced, allowing for high efficiency in industrial devices. Improved cleanliness in production lines, increased tool automation and improved production technology and cell architectures all helped to increase the efficiency of mainstream modules. Efficiency gains at the cell level were accompanied by an increase in wafer size and by the introduction of advanced assembly techniques. These improvements have allowed a reduction of cell-to-module efficiency losses and will accelerate the yearly efficiency gain of mainstream modules. To conclude, we discuss what it will take for other PV technologies to compete with silicon on the mass market.

(Invited) Detection of Dislocations Using X-Ray Diffraction Imaging (Topography) KOH Etching and Their Evolution after Epitaxial Growth in 4H-SiC

This work reports the characterization and analysis of various types of SiC substrate wafers by a high throughput (2 wafers/hour) X-ray diffraction imaging (XRDI) system. Quantitative maps of various dislocations are obtained using Automated Defect Classification (ADC) and correlated to other defect characterization methods including molten KOH etching and Photoluminescence (PL) scans. Different and often complementary views of the wafer were obtained by integrating the data. Epitaxial layers grown on the substrates show the probabilistic pattern of nucleation for various types of extended defects from defects in the underlying crystal structure. Nucleated Stacking Faults, especially, were well correlated with distributions of Basal Plane dislocations in the substrates.

Modeling and Control for Deadlock-Free Operation of Single-Arm Cluster Tools With Concurrently Processing Multiple Wafer Types via Petri Net

Nowadays, cluster tools tend to concurrently process multiple types of wafers with similar recipes in order to improve their utilization and flexibility in semiconductor manufacturing. Different wafer types may have different wafer flow patterns, resulting in that cluster tools are deadlock-prone. It is challenging to develop a general method to solve the deadlock problem of cluster tools without restriction on the wafer types. This work aims at solving such a challenging problem for single-arm cluster tools. To do so, a general Petri net model is developed for single-arm cluster tools. Given the wafer flow patterns of all wafer types to be processed in a single-arm cluster tool, such a Petri net model can be easily obtained by defining the relationship between places and transitions. Then, a control method by using self-loops is presented to prevent the model from deadlocks during the evolutions from the initial state to the final state. Furthermore, such a control method is proved to be optimal. Illustrative examples are given to verify the proposed method at last.

Reflectivity reduction of nanopatterned c-Si solar cells with antireflective coatings exposed to a wide range of incidence angles

The scope of the present study is to assess through numerical calculations the effect of nanopatterning the photovoltaics (PV) and that of imposing additional superstrate layers to the efficiency of the PV’s, under normal and wide incidence angles. The numerical calculations were performed with the Rigorous Coupled-Wave Analysis (RCWA) method where we examined several types of Si wafers including additional Si3N4 and SiO2 superstrate layers, and periodic patterns of grooves affecting either the superstrates or both the superstrates and Si substrate. A very broad parameter space was investigated (thickness of the superstrates, and the depth, diameter and periodicity constant of hole and pillar-like patterns) from which we derived the optimal set of parameters for each wafer type. The performance of the optimized wafers was then evaluated over a broad range of incident angles. Both the deposition of the superstrates as well as the imposition of periodic patterns improve drastically the absorption efficiency of the wafers and they allow for maintaining the maximum efficiency across the high incidence angle regime.

Design and Analysis of a Novel Piezoceramic Stack-based Smart Aggregate.

A novel piezoceramic stack-based smart aggregate (PiSSA) with piezoceramic wafers in series or parallel connection is developed to increase the efficiency and output performance over the conventional smart aggregate with only one piezoelectric patch. Due to the improvement, PiSSA is suitable for situations where the stress waves easily attenuate. In PiSSA, the piezoelectric wafers are electrically connected in series or parallel, and three types of piezoelectric wafers with different electrode patterns are designed for easy connection. Based on the theory of piezo-elasticity, a simplified one-dimensional model is derived to study the electromechanical, transmitting and sensing performance of PiSSAs with the wafers in series and parallel connection, and the model was verified by experiments. The theoretical results reveal that the first resonance frequency of PiSSAs in series and parallel decreases as the number or thickness of the PZT wafers increases, and the first electromechanical coupling factor increases firstly and then decrease gradually as the number or thickness increases. The results also show that both the first resonance frequency and the first electromechanical coupling factor of PiSSA in series and parallel change no more than 0.87% as the Young’s modulus of the epoxy increases from 0.5 to 1.5 times 3.2 GPa, which is helpful for the fabrication of PiSSAs. In addition, the displacement output of PiSSAs in parallel is about 2.18–22.49 times that in series at 1–50 kHz, while the voltage output of PiSSAs in parallel is much less than that in parallel, which indicates that PiSSA in parallel is much more suitable for working as an actuator to excite stress waves and PiSSA in series is suitable for working as a sensor to detect the waves. All the results demonstrate that the connecting type, number and thickness of the PZT wafers should be carefully selected to increase the efficiency and output of PiSSA actuators and sensors. This study contributes to providing a method to investigate the characteristics and optimize the structural parameters of the proposed PiSSAs.

Development of wafers with fillings made from organic raw materials with improved consumer properties

To improve the fatty acid and amino acid composition, as well as the organoleptic characteristics of flour confectionery products, new formulations for wafers Summer Temptation and Coconut Delight with fillings made from organic raw materials have been developed. Both products' formulations contain pure organic raw materials. The composition of Summer Temptation wafers includes buckwheat flour, cane sugar, butter, skimmed milk powder, sea buckthorn oil, and lemongrass powder. Rice flour, coconut sugar, dry coconut milk, coconut oil, lemongrass powder are added to the composition of Coconut Delight wafers. The developed products have excellent organoleptic characteristics that are confirmed by the conclusions from a tasting board. Safety indicators also comply with regulatory requirements. Both samples are distinguished by a lower content of heavy metals compared to control. Since the fatty base and flour were replaced in the new samples in comparison with the control formulation, the fatty acid and amino acid compositions of the products were investigated. The sample, based on organic buckwheat flour, demonstrated the best amino acid composition. The content of essential amino acids in the sample Coconut Delight increased slightly. The content of saturated fatty acids decreased by almost 1.5 times in both developed products. At the same time, the content of unsaturated fatty acids in both types of wafers increased by almost 4 times in comparison with control. These results indicate that the use of organic raw materials in the production of wafers with fillings improves their consumer properties. The addition of unconventional organic oils to the fillings improves the fatty acid composition while the replacement of flour in wafer sheets improves the amino acid composition. The obtained results can be used at enterprises in the food industry to expand the range of organic products

Processing Technology of Feed Wafer to Increase Feed Production and Efficiency

Feed is one of the important factor that affect livestock productivity, so the availability of good quality feed is a requirement for livestock development in an area. In the tropical area, providing forage as a crucial feed for ruminants was hampered by fluctuating seasons. Likewise, the availability of agricultural waste as an alternative source of feed material experiences the same constraints, easily damaged, and bulky (voluminous). Therefore, feed processing technology is needed so that it is become durable, easily stored, and easily provided for livestock. One way to overcome this is to utilize technology for making wafers. Information regarding technology for making animal feed wafers in Indonesia is still limited. This paper reviews a number of studies that discuss the development of wafer processing technology, types of wafers, the main components of wafer compilers, wafer manufacturing processes, reactions that occur during wafer manufacturing, nutrient quality of various wafers, and the results of research on the use of wafers for feed livestock. Wafers are feeds that are processed using heat and pressure, so that a solid, compact, and high density product is formed. Feed wafer technology is a modification of cube and block feed. Wafers are divided into feed wafers, feed supplement wafers, and complete feed wafers. Feed wafers can be used instead of concentrates. Feed supplement wafers are high in energy and protein. Complete feed wafers contain energy, protein, fiber, and complete minerals that have been adapted to the daily nutritional needs of livestock. Feed wafer processing technology can be one of the strategies to provide feed with a constant composition of nutrients throughout the season and increase production and feed efficiency.

Onset of ring defects in n-type Czochralski-grown silicon wafers

This paper presents experimental studies on the formation of ring defects during high-temperature annealing in both electronic-grade and upgraded metallurgical-grade (UMG) Czochralski-grown silicon wafers. Generally, a faster onset of ring defects, or shorter incubation time, was observed in the UMG samples ([Oi] = 6.3 × 1017 cm−3) in comparison to the electronic-grade samples ([Oi] = 3.9 × 1017 cm−3) used in this work. By applying a tabula rasa (TR) treatment prior to annealing, the incubation time can be increased for both types of wafers. We show that TR temperatures above 1000 °C are necessary to effectively dissolve grown-in oxygen precipitate nuclei and limit the subsequent formation of ring defects. A 30 min TR treatment at 1000 °C resulted in the longest incubation time for both types of samples used in this work, as it achieved the best balance between precipitate nuclei dissolution and precipitate re-growth/ripening. Finally, a nitrogen ambient TR step showed a short incubation time for the formation of ring defects in comparison to an oxygen ambient TR step.

Ultraviolet-B band lasers fabricated on highly relaxed thick Al0.55Ga0.45N films grown on various types of AlN wafers

In this paper, we investigated the dependence of threshold power density on the Al0.55Ga0.45N underlying layer film thickness in ultraviolet-B band (UV-B) lasers on various AlN wafers (four types). We also prepared and compared AlN templates for AlN freestanding substrates, AlN films fabricated by metalorganic vapor phase epitaxy, and annealed sputtered AlN templates at high temperature. The initial growth of AlGaN became three-dimensional by inserting a homoepitaxial Ga-doped AlN layer between the AlN template and Al0.55Ga0.45N, before it shifted to two-dimensional growth. It is possible to reduce the dislocation in Al0.55Ga0.45N using this mode. The dependence of AlGaN film thickness and that of the AlN template on samples with an inserted homoepitaxial Ga-doped AlN layer were studied. Compared with Al0.55Ga0.45N having a thickness of 5 μm, there was almost no noticeable difference between the dark spot density characterized by cathodoluminescence and the threshold power density in UV-B lasers for the AlN template. Besides, the characteristics were noticeably different for the film thickness of Al0.55Ga0.45N. The threshold power density in UV-B laser and dark spot density were reduced by increasing the film thickness. Through the optimization of the crystal growth condition, the threshold power density in UV-B laser and dark spot density were reduced to 36 kW cm−2 and 7.5 × 108 cm−2, respectively.

Investigation of the influence of the number of modules of a multicluster technological complex and the operations performed by them on the overall performance of the installation using simulation simulations

Variety of compositions of multicluster tools determines the development of methods aimed at analysis and search of feasible compositions, which meet the requirements and optimal performance (throughput) criteria. Very often in the industry, there is a task to find optimum utilization of the cluster tool. To find a solution various approaches are used, such as input in the system several flows of the semifinished products, increasing overall number of the arms of the robot, etc. In this article cluster tool and throughput dependence on quantity of performed operations of the least loaded module are investigated. It is shown, that with the help of this approach one can easily simplify both finding the solution of the task to composite cluster tool with flows of two different types of wafers and determining schedule of the wafers for maximum and minimum throughput. Relevance of the article is stipulated by substantive and complex choices of both finding optimal composition of the cluster tool and scheduling semifinished products flows (in accordance with variations of the operations in modules) at both the design and exploitation stage.

A Comparative Study of Three Types Shear Mode Piezoelectric Wafers in Shear Horizontal Wave Generation and Reception.

Guided wave-based inspection has emerged as a promising tool to evaluate the reliability of key components in modern industries. The fundamental shear horizontal (SH0) wave is always of great interests for plate-like structures because of its non-dispersion characteristics. However, the generation and reception of SH0 wave using piezoelectric wafers is not straightforward. In this paper, we firstly define three types shear mode piezoelectric wafers, i.e., the conventional in-plane poled thickness-shear (d15) mode, the thickness-poled thickness-shear (d15) mode, and the face-shear (d24) mode. Then, finite element simulations were conducted to demonstrate their performance in SH wave generation and reception. The results indicated that the face shear d24 wafer can generate almost single mode SH0 wave, while both types of d15 wafers would generate Lamb waves and SH0 wave simultaneously. Finally, experiments were carried out to check the efficiency of different shear mode piezoelectric wafers in SH0 wave generation and reception. The results indicated that the d24 wafer can generate and receive SH0 wave of high signal to noise ratio (SNR) with high energy conversion efficiency, while the in-plane poled d15 wafer would generate SH0 wave of high amplitude and acceptable SNR but with relatively low energy conversion efficiency. The performances of thickness-poled d15 wafer was not as good as the other two in both SH wave generation and reception. This work will be helpful for the applications of SH waves in plate-like structures.

A Wafer Prealignment Algorithm Based on Fourier Transform and Least Square Regression

Automatic wafer prealignment is an important process in wafer manufacturing, whereby its flat edge is set at a predefined angle and its center is set in a predefined position; translational and rotational movement compensate for deviation of the wafer. However, as the traditional wafer prealignment algorithm depends on marked templates at the training stage when the type of wafer is changed, the templates need to be retrained. This paper proposes a new wafer prealignment algorithm, based on Fourier transform for orientation prealignment and least square regression for position prealignment, which will automatically adapt to different types of wafers in 2-D space. Results from experiments with the proposed algorithm on a laser-scribing machine using two types of wafer show that the orientation prealignment achieved an accuracy of 0.05°, the position prealignment achieved an accuracy of 5 pixels, and the average operation time was approximately 1.5 s. As prealignment algorithm therefore meets real-time efficiency and precision requirements, it is suitable for use with semiconductor devices.

Multi-Wavelength Raman Characterization of Epitaxial Silicon Wafers for In-Line Process Characterization and Monitoring Applications

We have characterized 200-mm and 300-mm Si wafers with a single epitaxial layer and with a triple epitaxial layer stack atop using multi-wavelength, high-resolution Raman spectroscopy. 96-point wafer mapping measurements were performed on all wafers. Statistics of Raman signal intensity, shift and full-width-at-half-maximum (FWHM) values, under different excitation wavelengths, were extracted and compared with two types of reference Si wafers (prime Si wafers and reclaimed Si wafers). Significant variations in Raman signal intensity, shift and FWHM were measured between reference wafers and epitaxial wafers indicating potential Si lattice stress and crystallinity variations. Excitation wavelength dependence of Raman signal intensity, shift and FWHM also indicated variations in the Si lattice stress and the crystallinity of epitaxial layers in the depth direction. Non-contact multiwavelength Raman spectroscopy was found to be very sensitive to the quality of epitaxial Si layers which makes this technique very effective in complimentary in-line process characterization and monitoring.