Types Of Transistors Research Articles

Analysis of radiation effects of semiconductor devices based on numerical simulation Fermi–Dirac

Abstract To study the radiation effect of Fermi–Dirac (F–D) semiconductor devices based on numerical simulation, two methods are used. One is based on the combination of F–D statistical method and computer simulation. The method discusses the influence of temperature and light energy on the carrier number by starting from an intrinsic silicon semiconductor and carries out computer simulation on the carrier number in intrinsic silicon semiconductor. TID Sim, a three-dimensional parallel solver for ionizing radiation effects of semiconductor devices, is developed. The ionization radiation damage of typical metal oxide semiconductor (MOS) FET NMOS and bipolar transistor GLPNP is simulated. It was proved that the variation trend was close to a straight line in the temperature range (278–358 K) studied in this article. The results are consistent with those of the statistical distribution of semiconductor carriers. This method is suitable for calculating the number of semiconductor carriers, and it is an effective method to study the problems related to carrier distribution.

Certain Aspects of Quantum Transport in Zigzag Graphene Nanoribbons

We have investigated the Fano factor and shot noise theoretically in the confined region of the potential well of zigzag graphene nanoribbon (ZGNR). We have found that the Fano factor is approximately 1, corresponding to the minimum conductivity (σ) for both symmetrical and asymmetrical potential wells. The conductivity plot with respect to Fermi energy appears as symmetrical plateaus on both sides of zero Fermi energy. Moreover, a peak observed at zero Fermi energy in the local density of states (LDOS) confirms the edge states in the system. The transmission properties of ZGNR in the confined region of the potential well are examined using the standard tight-binding Green’s function approach. The perfect transmission observed in the confined region of the potential well shows that pnp type transistors can be made with ZGNR. We have discussed the Fano factor, shot noise, conductivity, and nanohub results in the continuation of previous results. Our results show that the presence of van-Hove singularities in the density of states (DOS) matters in the presence of edge states. The existence of these edge states is sensitive to the number of atoms considered and the nature of the potential wells. We have compared our numerical results with the results obtained from the nanohub software (CNTbands) of Purdue University.

A novel stair‐finger grid type transistor for high‐performance millimeter‐wave power amplifier

A novel stair-finger grid type (SFGT) transistor layout is proposed in this letter to improve the f T ${f}_{{\rm{T}}}$ and f max ${f}_{\max }$ of large-sized transistors for the millimeter-wave power amplifier (PA). It combines the promoted stair-finger transistor cells in a grid pattern to minimize parasitic capacitances and metal losses, which has been verified to provide higher gain over broadband by measurements. Two three-stage dual-differential PAs with different transistor layouts are compared in this letter. The PA employs a capacitive neutralization technique and distributed active transformer-based combiner and divider. Fabricated in the Huali Microelectronics Corporation (HLMC) 40-nm Complementary Metal Oxide (CMOS) (Co process, the PA with SFGT transistor [PA2] achieves higher gain and output power than the PA with the currently best-known transistor [PA1]). PA2 achieves 15.22 dBm saturated output power ( P sat ${P}_{\mathrm{sat}}$ ), 14.25 dBm output power at 1 dB compression point ( P 1 dB ${P}_{1\unicode{x0200A}\mathrm{dB}}$ ), and 18.09 dB power gain when the basic supply is 1.1 V at 83 GHz.

Hours-Long Transient Leakage Current in MOS Structures Induced by High Total-Ionizing-Dose

This article studies the apparition and the fast annealing of a leakage current in p- and n-MOS transistors and structures. This leakage current is observed for total ionizing doses (TIDs) of 50 Mrad(SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ) and above and anneals rapidly within the hours following the end of irradiation. An extensive set of specially designed and dedicated structures are used to study this phenomenon. In particular, the article presents the effects of the dose rate, the transistor type (n or p), the drain–source voltage, or the bias during annealing. Results show that the observed transient leakage current is an intensification followed by fast annealing of the generation current inside the drain and source depletion regions. It appears that this generation leakage current most likely originates from the creation of positive charges in the thick oxides of the devices, that is, the shallow trench isolation (STI) and the pre-metal dielectric (PMD), and it generally anneals at ambient temperature in less than 12 h after irradiation.

TRANSIT TIME MODEL ANALYSIS THROUGH THE BASIS IN THE CASE OF DRIFT TRANSISTORS HBT

The manufacturing technology for heterojunction bipolar transistor (HBT) is different from the one used for bipolar silicon junction transistor (BJT). The base in case of BJT is manufactured by using diffusion and the diffusion laws determine a Gaussian type of profile in the base. HBT devices are manufactured using molecular epitaxy which gives a contact doping profile. In case of HBT, producing an internal field by using uniform doping is no more possible. This is the reason why was used in the gradation of the molar composition. The Analysis using Octave soft was made for the transit time through the base of the drift HBT transistors type GaAs/AlxGa1-xAs.

Double injection function InGaZnO transistor—computational analysis of the patterned doping method

Metal oxide-based electronics is advancing rapidly where the reduced dimensions require transistor structures different to conventional CPUs. The double injection function transistor (DIFT) is a type of a source-controlled transistor. As doping is a facile method in the semiconductor industry, we suggest that the DIFT can be realized through a doping pattern under the source electrode. We show that double doping functions similarly to the double work function DIFT, recently demonstrated. We use device simulations to analyze the operation principle of the DIFT structure and provide design guidelines. We find that the structural separation of the injection and depletion functions allows adapting the transistor structure to fabrication process limitations. A 200 nm channel length InGaZnO based device can be designed to exhibit proper saturation at sub-1 V drain bias.

OFET and OECT, Two Types of Organic Thin-Film Transistor Used in Glucose and DNA Biosensors: A Review

Due to their advantages of low cost, flexibility, ease of manufacture and biocompatibility, organic thin film transistor (OTFT) hold great commercial potential. Specifically, there are two types of OTFT, OFET and OECT, which are widely used in the field of flexible biological sensors and have great ability for glucose and DNA detection of diabetes. In this paper, we describe the working principles of OFET and OECT, and compare the differences between them. Some examples are given and clarified, including the materials, fabrication and chemical reactions. There is still a lot of space to be explored in OTFT for other biomarker sensing applications. With the emergence of new materials and fabrication techniques, OTFT-based biosensor would be more widely used in diagnostic equipment to improve patient outcomes.

GO-HFIPPH covered a-IGZO thin film transistor for gate tunable DMMP detection

Field-effect transistor (FET) type gas sensors are showing their great attractions to researchers due to their miniature size, gate tunable sensitivity and compatibility with CMOS technology. Amorphous indium gallium zinc oxide (a-IGZO) thin film transistors have the advantage of simple preparation method, high mobility and potential for large-scale integration, which has been widely investigated in recent years. The traditional method of obtaining selectivity of semiconductor sensing materials is to make chemical decorations directly to the semiconductor active layer, which may damage the material’s properties. In this paper, we decorate graphene oxide (GO) with p-hexafluoroisopropanol phenyl (HFIPPH) to form GO-HFIPPH, and then use GO-HFIPPH to physically modify a-IGZO TFT through self-assembly to prepare a FET-type dimethyl methylphosphonate (DMMP) sensor. The proposed sensor shows good sensitivity and selectivity to DMMP, and has a 61.1 nA response to 200 ppb DMMP with 42 s and 26 s response/recovery time. In addition, the sensing mechanism is explained based on hydrogen bond theory, heterojunction and charge transportation of the a-IGZO transistor. We believe our GO-HFIPPH/a-IGZO TFT DMMP sensor will show a significant value for FET-type gas sensor design.

Single-Branch Wide-Swing-Cascode Subthreshold GaN Monolithic Voltage Reference

A voltage reference generator in GaN IC technology for smart power applications is described, analyzed, and simulated. A straightforward design procedure is also highlighted. Compared to previous low-power monolithic solutions, the proposed one is based on a single branch and on transistors operating in a subthreshold. The circuit provides a nearly 2.7 V reference voltage under 4 V to 24 V supply at room temperature and with typical transistor models. The circuit exhibits a good robustness against large process variations and improves line regulation (0.105 %V) together with a reduction in area occupation (0.05 mm2), with a reduced current consumption of 2.7 µA (5 µA) in the typical (worst) case, independent of supply. The untrimmed temperature coefficient is 200 ppm/°C.

Design and Fabrication of Electrostatically Formed Nanowire Gas Sensors With Integrated Heaters

This work reports on the design and fabrication of planar gas sensors with membrane structure to allow in-situ heating capabilities crucial for enhancing gas sensing performances. The sensors are virtual nanowire field-effect transistor (FET) type devices, referred to as electrostatically formed nanowire (EFN) sensors. This work describes the design, fabrication, and performance of a 2 mm X 2 mm chip with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$850 ~\mu \text{m}$ </tex-math></inline-formula> diameter, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3.5 ~\mu \text{m}$ </tex-math></inline-formula> thick membrane. The design has been analyzed using finite element simulations (FEM) and verified experimentally. The thermal efficiency of the heated membrane is found to be 10 mW to reach 400 °C, which is better than most of the reported membrane-based sensors. To improve sensitivity and for broader functionality, the sensing surface, unlike reported in most designs, is at the bottom of the membrane. The technology allows system on chip (SoC) integration and further can be used for the fabrication of handheld battery-operated gas detectors. [2021-0248]

Klasifikasi Citra Jenis Kapasitor Menggunakan Kombinasi Algoritma K-Nearest Neighbor dan Principal Component Analysis

To learn about electronic devices, one must know about the types of electronic components. Capacitors are one of several important electronic components. Capacitors are part of passive components that are able to store energy or electric charge at a temporary time. Capacitors or commonly called capacitors have many types. However, some people do not know about these types of capacitors. Especially for someone or a student who will learn about electronic components. The purpose of this study is to develop a digital image processing system for the classification of transistor types by applying the K-Nearest Neighbor (KNN) and Principal Component Analysis (PCA) methods. PCA serves to reduce and retain most of the relevant information from the original features according to the optimal criteria. Based on the results of feature extraction and data reduction performed by PCA, it is easier for the KNN algorithm to classify. KNN performs a classification based on the data closest to the object being processed. Based on the test results, the developed model is able to produce an average accuracy value of 82.50%. This means that PCA and KNN algorithms can be used in the process of classifying capacitor type images properly

Electric‐Field‐Tunable Bandgaps in the Inverse‐Designed Nanoporous Graphene/Graphene Heterobilayers

AbstractThe recent bottom‐up synthesis of atomically precise nanoporous graphene (NPG) offers a way of tuning graphene's properties by forming NPG/graphene (Grp) bilayers. Depending on the size, shape, and periodicity of the nanopores in NPG, the heterobilayers can exhibit various functionalities. This theoretical work presents an inverse design of NPG/Grp bilayers with electric‐field‐tunable bandgaps as a target property. The interlayer interaction in such heterobilayers can induce a bandgap in graphene either by breaking inversion symmetry (type I) or by moving and merging Dirac points of graphene (type II). The bandgap opening also requires electron–hole symmetry breaking induced by an applied perpendicular electric field, leading to two distinct, linear versus nonlinear, field dependences of the bandgap for the type‐I and type‐II cases, respectively. To translate the underlying physics of the bandgap opening in graphene into real atomic structures, the authors develop an inverse design method and find NPG/Grp bilayers with the target functionality. The field‐tunable bandgap in graphene, supported by first‐principles calculations for the inverse‐designed systems, holds promise for new types of graphene transistors.

Gated-CNN: Combating NBTI and HCI aging effects in on-chip activation memories of Convolutional Neural Network accelerators

Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) are two of the main reliability threats in current technology nodes. These aging phenomena degrade the transistor’s threshold voltage (Vth) over the lifetime of a digital circuit, resulting in slower transistors that eventually lead to a faulty operation when the critical paths become longer than the processor cycle time. Among all the transistors on a chip, the most vulnerable transistors to such wearout effects are those used to implement SRAM storage, since memory cells are continuously degrading. In particular, NBTI ages PMOS cell transistors when a given logic value is stored for a long period (i.e., a long duty cycle), whereas HCI ages NMOS cell transistors not only when the stored value flips but also when it is accessed. This work focuses on mitigating aging in the on-chip SRAM memories of Convolutional Neural Network (CNN) accelerators storing activations. This paper makes two main contributions. At the software level, we quantify the aging induced by current CNN benchmarks with a characterization study of duty cycle, flip, and access patterns in every activation memory cell. Based on the insights from this study, this work proposes a novel microarchitectural technique, Gated-CNN, that ensures a uniform aging degradation of every memory cell. To do so, Gated-CNN exploits power-gating and address rotation techniques tailored to the memory demands and temporal/spatial localities exhibited by CNN applications, as well as the memory organization and management of CNN accelerators. Experimental results show that, compared to a conventional design, the average Vth degradation savings are at least as much as 49% depending on the type of transistor.

High-κ perovskite membranes as insulators for two-dimensional transistors.

The scaling of silicon metal-oxide-semiconductor field-effect transistors has followed Moore's law for decades, but the physical thinning of silicon at sub-ten-nanometre technology nodes introduces issues such as leakage currents1. Two-dimensional (2D) layered semiconductors, with an atomic thickness that allows superior gate-field penetration, are of interest as channel materials for future transistors2,3. However, the integration of high-dielectric-constant (κ) materials with 2D materials, while scaling their capacitance equivalent thickness (CET), has proved challenging. Here we explore transferrable ultrahigh-κ single-crystalline perovskite strontium-titanium-oxide membranes as a gate dielectric for 2D field-effect transistors. Our perovskite membranes exhibit a desirable sub-one-nanometre CET with a low leakage current (less than 10-2 amperes per square centimetre at 2.5 megavolts per centimetre). We find that the van der Waals gap between strontium-titanium-oxidedielectricsand 2D semiconductors mitigates the unfavourable fringing-induced barrier-lowering effect resulting from the use of ultrahigh-κ dielectrics4. Typical short-channel transistors made of scalable molybdenum-disulfidefilms by chemical vapour deposition and strontium-titanium-oxide dielectrics exhibit steep subthreshold swings down to about 70 millivolts per decade and on/off current ratios up to 107, which matches the low-power specifications suggested by the latest International Roadmap for Devices and Systems5.

Manipulating high-temperature superconductivity by oxygen doping in Bi2Sr2CaCu2O8+δ thin flakes.

Harnessing the fascinating properties of correlated oxides requires precise control of their carrier density. Compared to other methods, oxygen doping provides an effective and more direct way to tune the electronic properties of correlated oxides. Although several approaches, such as thermal annealing and oxygen migration, have been introduced to change the oxygen content, a continuous and reversible solution that can be integrated with modern electronic technology is much in demand. Here, we report a novel ionic field-effect transistor using solid Gd-doped CeO2 as the gate dielectric, which shows a remarkable carrier-density-tuning ability via electric-field-controlled oxygen concentration at room temperature. In Bi2Sr2CaCu2O8+δ (Bi-2212) thin flakes, we achieve a reversible superconductor-insulator transition by driving oxygen ions in and out of the samples with electric fields, and map out the phase diagram all the way from the insulating regime to the over-doped superconducting regime by continuously changing the oxygen doping level. Scaling analysis indicates that the reversible superconductor-insulator transition for the Bi-2212 thin flakes follows the theoretical description of a two-dimensional quantum phase transition. Our work provides a route for realizing electric-field control of phase transition in correlated oxides. Moreover, the configuration of this type of transistor makes heterostructure/interface engineering possible, thus having the potential to serve as the next-generation all-solid-state field-effect transistor.

Near infrared light-sensing semi-transparent organic phototransistors with soluble benzothiadiazole-based conjugated polymer films

Here we report semi-transparent organic phototransistors (OPTRs), which consist of poly[{3-(5-(7-methyl-5,6-bis(octyloxy)benzo[c][1,2,5]thiadiazol-4-yl)thiophen-2-yl)-6-(5-methylthiophen-2-yl)}-co-{2,5-bis(2-octyldodecyl)-2,5-dihydropyrrolo[3,4-c]pyrrole-1,4-dione}] (PDPP-8OBT) as a sensing channel layer, for the detection of particular near infrared (NIR) light (905 nm) that is used in the light and distance ranging (LiDAR) systems. Two different thicknesses (45 and 75 nm) were chosen for the examination of NIR light-sensing performances, while both ca. 20 nm-thick silver source/drain electrodes and transparent indium-tin oxide (ITO) gate electrodes were applied to achieve the semi-transparency of devices. Results showed that the present devices could be operated in a mode of typical p-channel transistor and were sensitive to the NIR light. The semi-transparent OPTRs with the 75 nm-thick PDPP-8OBT layers showed better NIR light-sensing performances with the high photosensitivity of ca. 200 %. The performance of devices was slightly varied by running about 50 cycles of transfer curves between forward and backward sweeps, whereas the NIR light-sensing characteristics were well kept during the cycle tests. It is expected that the present NIR-OPTRs with the PDPP-8OBT sensing channel layers can be applied as a practical detector for LiDAR systems through further optimization of device stability.

Detection of Stress Hormone with Semiconducting Single-Walled Carbon Nanotube-Based Field-Effect Transistors

Non-invasive detection and quantification of the stress hormone cortisol not only provide the assessment of stress level but also enable close monitoring of mental and physical health. In this work, we report two types of field-effect transistors (FETs) based on semiconducting single-walled carbon nanotubes (sc-SWCNTs) as selective cortisol sensors. In one FET device configuration cortisol antibody is directly attached to sc-SWCNTs, the other one is using gold nanoparticles (Au NPs) as linkers in between antibody and sc-SWCNTs to enhance the device conductance. We fabricated and characterized both device configurations to investigate how the nanomaterial interface to cortisol antibody influences the biosensor performance. We tested the sensors in artificial sweat and compared these two types of sensors in terms of limit of detection and sensitivity, and the results indicate that direct binding between antibody and sc-SWCNTs yields better biosensor characteristics.

Effect of Hydrogen Migration in SiO2/Al2O3 Stacked Gate Insulator of InGaZnO Thin-Film Transistors

In this work, the correlation between SiO2 deposition thickness and hydrogen content is discussed and the effect of the SiO2 layer on the properties of synaptic InGaZnO (IGZO) TFTs is analyzed. Three types of IGZO synaptic thin-film transistors (TFTs) were fabricated with different gate insulators, and the effect of SiO2 as a gate insulator was investigated. XPS analysis confirmed that the hydrogen content in the Al2O3 and SiO2 layers increased during SiO2 deposition step for all depth regions. Hydrogen injected by the SiO2 layer deposition step was confirmed to improve the memory window through more threshold voltage shift under positive bias stress (PBS) and negative bias stress (NBS) conditions. In addition, the retention characteristics were improved due to the low hydrogen movement velocity in the SiO2 layer. These results contribute to the optimization of the amount of hydrogen, and the proposed device has potential as a synaptic device capable of neuromorphic computing.

Dynamic Model of the Short-Term Synaptic Behaviors of PEDOT-based Organic Electrochemical Transistors with Modified Shockley Equations.

Neuromorphic computing is an emerging area with prospects to break the energy efficiency bottleneck of artificial intelligence (AI). A crucial challenge for neuromorphic computing is understanding the working principles of artificial synaptic devices. As an emerging class of synaptic devices, organic electrochemical transistors (OECTs) have attracted significant interest due to ultralow voltage operation, analog conductance tuning, mechanical flexibility, and biocompatibility. However, little work has been focused on the first-principal modeling of the synaptic behaviors of OECTs. The simulation of OECT synaptic behaviors is of great importance to understanding the OECT working principles as neuromorphic devices and optimizing ultralow power consumption neuromorphic computing devices. Here, we develop a two-dimensional transient drift–diffusion model based on modified Shockley equations for poly(3,4-ethylenedioxythiophene) (PEDOT)-based OECTs. We reproduced the typical transistor characteristics of these OECTs including the unique non-monotonic transconductance–gate bias curve and frequency dependency of transconductance. Furthermore, typical synaptic phenomena, such as excitatory/inhibitory postsynaptic current (EPSC/IPSC), paired-pulse facilitation/depression (PPF/PPD), and short-term plasticity (STP), are also demonstrated. This work is crucial in guiding the experimental exploration of neuromorphic computing devices and has the potential to serve as a platform for future OECT device simulation based on a wide range of semiconducting materials.

Current source gate drivers for 3-phase VSI operated in small-scale wind turbine systems

The paper is dedicated to the improvement of efficiency of small-scale wind turbines’ (SSWT) power electronic converters. An efficiency of the 3-phase voltage source inverter that operates with low output voltage (<60 V) and high grid-side input voltage (380 V) is investigated. Such a solution allows skipping the intermediate DC/DC boost converter and thus reducing conversion losses and complexity of a system. The inverter has to oaperate with low duty cycles, which, in turn, demands increasing of switching speed and thus requires application of advanced transistors. To evaluate the switching performance, studies were carried out with various types of switches, namely Si IGBT, Si MOSFET, Cascode SiC JFET, SiC MOSFET using classic gate drivers and proposed current source drivers. Detailed switching waveforms were obtained using the double pulse method and analyzed for each type of the switch. The switching speed was assessed and losses were evaluated. Two types of transistors were selected for testing in the VSI paired with an EMRAX 228 generator. Inverter efficiency data was obtained and analyzed for two types of transistors/drivers and the speed-torque curve applicable for a 3 kW turbine. It is shown that the suggested solution improves the efficiency of SSWTs’ inverters.