A novel stair-finger grid type (SFGT) transistor layout is proposed in this letter to improve the f T ${f}_{{\rm{T}}}$ and f max ${f}_{\max }$ of large-sized transistors for the millimeter-wave power amplifier (PA). It combines the promoted stair-finger transistor cells in a grid pattern to minimize parasitic capacitances and metal losses, which has been verified to provide higher gain over broadband by measurements. Two three-stage dual-differential PAs with different transistor layouts are compared in this letter. The PA employs a capacitive neutralization technique and distributed active transformer-based combiner and divider. Fabricated in the Huali Microelectronics Corporation (HLMC) 40-nm Complementary Metal Oxide (CMOS) (Co process, the PA with SFGT transistor [PA2] achieves higher gain and output power than the PA with the currently best-known transistor [PA1]). PA2 achieves 15.22 dBm saturated output power ( P sat ${P}_{\mathrm{sat}}$ ), 14.25 dBm output power at 1 dB compression point ( P 1 dB ${P}_{1\unicode{x0200A}\mathrm{dB}}$ ), and 18.09 dB power gain when the basic supply is 1.1 V at 83 GHz.