Two-dimensional Device Simulation Research Articles

BJT-based detector on high-resistivity silicon with integrated biasing structure

A novel method for biasing phototransistor-based radiation detectors on high-resistivity Si is presented, that relies on the integration into the detector base of a pnp transistor acting as a current source. The proposed approach can be extended in a natural way to the biasing of npn detector arrays, allowing different detectors to be biased at the same quiescent current, by connecting all the biasing pnp transistors with a diode-connected reference transistor (integrated onto the same chip), so that they form a current-mirror circuit. Relying on two-dimensional numerical device simulations, several test structures have been designed and fabricated, including single BJT detectors and detector arrays with pnp biasing transistors connected in the current-mirror configuration. The electrical characterization of fabricated structures shows that both single detectors and detector arrays are operational and behave in good agreement with simulations, thus demonstrating the feasibility of the proposed approach.

Leakage Current Reduction Techniques in Poly-Si TFTs for Active Matrix Liquid Crystal Displays: A Comprehensive Study

This paper critically examines the leakage current reduction techniques for improving the performance of polycrystalline silicon (poly-Si) thin-film transistors (TFTs) used in active matrix liquid crystal displays. This is a first comprehensive study in literature on this topic. The review assesses important proposals to circumvent the leakage current problem in poly-Si TFTs and a short evaluation of strengths and weaknesses specific to each method is presented. Also, a new device structure called the triple-gate poly-Si TFT (TG-TFT) is discussed. The key idea in the operation of this device is to make the dominant conduction mechanism in the channel to be controlled by the accumulation charge density modulation by the gate and not by the gate-induced grain barrier lowering. Using two-dimensional and two-carrier device simulation, it is demonstrated that the TG-TFT exhibits a significantly diminished pseudosubthreshold conduction leading to several orders of magnitude reduction in the OFF-state leakage current when compared with a conventional poly-Si TFT. The reasons for the improved performance are explained

Adjustable high-speed insulated gate bipolar transistor

A new adjustable insulated gate bipolar transistor (IGBT) with Si/SiGe heterojunction collector structures is proposed to improve the operation speed and decrease the turnoff power loss by suppressing the tail-current. SiGe collector provides low contact resistance without consequently sacrificing turnoff losses, and also acts to suppress hole-injection into drift region during on-state and accelerate the clear sweep of the holes when the device is cutoff. On the other hand, turn-on voltage loss is increased due to the use of SiGe collector. This drawback can be minimized by using lower percentages of Ge in SiGe, since the potential barrier height at the Si/SiGe junction is controlled by the percentage of Ge in SiGe, which means the proposed IGBT can be tuned freely to meet different needs by means of changing the percentage of Ge region in the SiGe. Further, the proposed IGBT exhibits a more superior on-state/switching tradeoff relation when compared to the conventional IGBT. Two-dimensional device and circuit mixed-mode simulations are also performed to offer valuable information about the internal dynamical mechanisms of these devices, thus improving the understanding of device performance in SiGe collector applications

Enhanced Breakdown Voltage, Diminished Quasi-Saturation, and Self-Heating Effects in SOI Thin-Film Bipolar Transistors for Improved Reliability: A TCAD Simulation Study

Based on an extensive two-dimensional process and device simulation studies, a new n/sup +/-p-n-n/sup +/ vertical submicrometer bipolar junction transistor with a three-zone step doped lateral collector (VSLC) structure is presented. It is demonstrated for the first time that the breakdown voltage of the thin-film (<0.5 /spl mu/m) bipolar transistors can be enhanced significantly by using a combination of a vertical thin base and the VSLC structure. The proposed VSLC structure exhibits: 1) excellent output characteristics; 2) diminished quasi-saturation; 3) improved reliability against self-heating effect; and 4) enhanced breakdown voltage as high as 60% more than that of the conventional thin-film lateral bipolar transistor (LBT) on silicon-on-insulator. It also obviates the difficulties associated with the formation of a thin base in LBTs.

On the scaling limit of ultrathin SOI MOSFETs

In this paper, a detailed study on the scaling limit of ultrathin silicon-on-insulator (SOI) MOSFETs is presented. Due to the penetration of lateral source/drain fields into standard thick buried oxide, the scale-length theory does not apply to thin SOI MOSFETs. An extensive two-dimensional device simulation shows that for a thin gate insulator, the minimum channel length can be expressed as L/sub min//spl ap/4.5(t/sub Si/+(/spl epsiv//sub Si///spl epsiv//sub I/)t/sub I/), where t/sub Si/ is the silicon thickness, and /spl epsiv//sub I/ and t/sub I/ are the permittivity and thickness of the gate insulator. With t/sub Si/ limited to /spl ges/ 2 nm from quantum mechanical and threshold considerations, a scaling limit of L/sub min/=20 nm is projected for oxides, and L/sub min/=10 nm for high-/spl kappa/ dielectrics. The effect of body doping has also been investigated. It has no significant effect on the scaling limit.

Compact modeling of the effects of parasitic internal fringe capacitance on the threshold voltage of high-k gate-dielectric nanoscale SOI MOSFETs

A compact model for the effect of the parasitic internal fringe capacitance on the threshold voltage of high-k gate-dielectric silicon-on-insulator MOSFETs is developed. The authors' model includes the effects of the gate-dielectric permittivity, spacer oxide permittivity, spacer width, gate length, and the width of an MOS structure. A simple expression for the parasitic internal fringe capacitance from the bottom edge of the gate electrode is obtained and the charges induced in the source and drain regions due to this capacitance are considered. The authors demonstrate an increase in the surface potential along the channel due to these charges, resulting in a decrease in the threshold voltage with an increase in the gate-dielectric permittivity. The accuracy of the results obtained using the authors' analytical model is verified using two-dimensional device simulations.

AlGaN/GaN High Electron Mobility Transistors with Inclined-Gate-Recess Structure

We have studied an inclined-gate-recess structure in order to clarify the effect of increasing the electric field in the channel. Two-dimensional device simulation has revealed that the electric field and the electron velocity in the channel have increased by the inclined-gate-recess structure, which leads to an improvement of gm. AlGaN/GaN high electron mobility transistors (HEMTs) with inclined-gate-recess have been fabricated. Improved gm and fT have been obtained, which confirms the importance of increasing the electric field in the channel.

Lateral profiling of trapped charge in SONOS flash EEPROMs programmed using CHE injection

The lateral profile of trapped charge in a silicon-oxide-nitride-oxide-silicon (SONOS) electrically erasable programmable read-only memory programmed using channel-hot-electron injection is determined using current-voltage (I/sub D/-V/sub G/) measurements along with two-dimensional device simulations and is verified using gate-induced-drain-leakage measurements, charge-pumping (CP) measurements, and Monte Carlo simulations. An iterative procedure is used to match simulated I/sub D/-V/sub G/ characteristics with experimental I/sub D/-V/sub G/ characteristics at different stages of programming, by sequentially increasing the trapped electron charge in simulations. Fresh cells are found to contain a high laterally nonuniform trapped charge, which (along with large electron injection during the program) make the conventional CP techniques inadequate for extracting the charge profile. This charge results in a nonmonotonous variation of threshold and flat-band voltages along the channel and makes it impossible to simultaneously determine interface and trapped charge profiles using CP alone. The CP technique is modified for application to SONOS cells and is used to verify the charge profile obtained using I/sub D/-V/sub G/ and to estimate the interface degradation. This paper enhances the study presented in our earlier work.

New fundamental insights into capacitance modeling of laterally nonuniform MOS devices

In compact transistor modeling for circuit simulation, the capacitances of conventional MOS devices are commonly determined as the derivatives of terminal charges, which in their turn are obtained from the so-called Ward-Dutton charge partitioning scheme. For devices with a laterally nonuniform channel doping profile, however, it is shown in this paper that no terminal charges exist from which the capacitances can be derived. Instead, for such devices, a new model is presented for the capacitances themselves. Furthermore, a method is given to incorporate such a capacitance model into circuit simulators, which are traditionally based on terminal charge models. Comparison with two-dimensional device simulations and a segmentation model shows that for a constant mobility, the new capacitance model provides an accurate description for a MOSFET with a laterally diffused channel doping profile. Through a comparison with high-frequency measurements, the agreement between model and experimental results is discussed.

Threshold voltage sensitivity to doping density in extremely scaled MOSFETs

The dependence of the threshold voltage (VT) on channel doping for extremely scaled devices is investigated. This work is focused on the fundamental VT issue and its physical insight into the impact of the doping density on device characteristics. We find that the threshold voltage is, in fact, insensitive to doping over a wide range of doping density and such insensitivity is further extended by bandgap narrowing in nanoscale MOSFETs via analytical analyses and two-dimensional numerical device simulations (2003 Taurus-MEDICI User Guide (Mountain View, CA: Synopsis Inc.)). This result particularly suggests the scalability and feasibility of nanoscale double-gate MOSFETs.

Device Simulation and Design Optimization for Diamond Based Insulated-gate Bipolar Transistors

ABSTRACTA diamond based insulated gate bipolar transistor is incorporated into a two-dimensional device simulator (MEDICI) to examine the current gain (β) and potential distribution across the device. Initially, work has focused on an important component of IGBT structure, the PNP bipolar transistor, which has been simulated and is reported upon in this paper. Empirical parameters for emitter and collector regions were used. Various carrier concentrations for base region were used to optimize the simulation. It was found that decreasing the thickness of base region leads to an increase in current gain. A buffer layer is needed to prevent the punch-through at low carrier concentration in the base region. Various approaches of increasing the current gain are also discussed in this paper.

표면 도핑 기법을 사용한 SOI RESURF LDMOSFET의 항복전압 및 온-저항 특성 분석

In this paper, breakdown voltage and on-resistance characteristics of the surface doped SOI RESURF LDMOSFET were investigated as a function of surface doping depth. In order to verify the variation of characteristics, two-dimensional device simulation was carried out. Breakdown voltage of the proposed structure is varied from <TEX>$73 {\~}138V$</TEX> while surface doping depth varied from <TEX>$0.5{\~}2.0{\mu}m$</TEX>. And on-resistance is decreased from <TEX>$0.18{\~}0.143{\Omega}/cm^2$</TEX> while surface doping depth increased from <TEX>$0.5 {\~}2.0{\mu}m$</TEX>. Maximum breakdown voltage of the proposed structure is 138 V at <TEX>$1.5{\mu}m$</TEX> depth of surface doping, yielding <TEX>$22.1\%$</TEX> of improvement of breakdown voltage in comparison with that of the conventional SOI RESURF LDMOSFET with same epi-layer concentration. On-resistance characteristic is also improved about <TEX>$21.7\%$</TEX>.

Two-dimensional methodology for modeling radiation-induced off-state leakage in CMOS technologies

A modeling approach using two-dimensional device simulations is presented, which enables the extraction of parameters for the radiation-induced parasitic MOSFET created at the edge of the shallow trench isolation (STI) oxide. With the model, one can estimate drain-to-source off-state leakage current (I/sub OFF/) resulting from build-up of oxide trapped charge (N/sub OT/). The impact of nonuniform N/sub OT/ build-up in the STI resulting from total ionizing dose (TID) exposure and external bias conditions is analyzed through volumetric simulations and compared to experimental data. Saturation for the off-state leakage current as a function of trapped charge is also investigated.

The Influence of Source and Drain Junction Depth on the Short-Channel Effect in MOSFETs

This brief investigates the influence of source and drain junction depth on the short-channel effect (SCE) in highly scaled MOSFETs. The established scale length model represents SCE in terms of an exponential function of gate insulator thickness and gate depletion-layer width, but this model fails to account for any influence of source and drain junction depth on SCE. It is shown using two-dimensional finite-element device simulation that the influence of source and drain junction depth on SCE can be represented by an addition of a pre-exponential term to the established scale-length model. For source and drain junction depths that are deeper than the MOSFET's gate depletion-layer width, SCE is shown with this pre-exponential term to be insensitive to junction depth. Conversely, for source and drain junction depths that are shallower than the MOSFET's gate depletion-layer width, SCE is shown to improve linearly with decreasing junction depth.

The Simulation of a new asymmetrical double-gate poly-Si TFT with modified channel conduction mechanism for highly reduced OFF-state leakage current

Poly-Si thin film transistors (TFTs) exhibit large OFF-state reverse leakage currents since their channel conduction is controlled by the gate-induced grain barrier lowering (GIGBL). This also leads to the presence of the pseudosubthreshold region in the transfer characteristic. In this paper, we report a novel poly-Si multiple-gate TFT (MG-TFT), where the front gate consists of three sections with two different materials, in order to reduce the OFF-state leakage current with no significant change in the ON-state current. We demonstrate that the dominant conduction mechanism in the channel can be controlled entirely by the accumulation charge density modulation by the gate (ACMG) instead of the GIGBL, leading to a steep subthreshold slope without any pseudosubthreshold region when compared to an asymmetrical double-gate poly-Si TFT (DG-TFT), resulting in a significantly reduced OFF-state leakage current. Using two-dimensional (2-D) and two-carrier device simulation, we have analyzed the various performance and design considerations of the MG-TFT and explained the reasons for the improved performance of the MG-TFT.

A new symmetrical double gate nanoscale MOSFET with asymmetrical side gates for electrically induced source/drain

In this paper, we present the unique features exhibited by a novel double gate MOSFET in which the front gate consists of two side gates as an extension of the source/drain. The asymmetrical side gates are used to induce extremely shallow source/drain regions on either side of the main gate. Using two-dimensional and two-carrier device simulation, we have investigated the improvement in device performance focusing on the threshold voltage roll-off, the drain induced barrier lowering, the subthreshold swing and the hot carrier effect. Based on our simulation results, we demonstrate that the proposed symmetrical double gate SOI MOSFET with asymmetrical side gates for the induced source/drain is far superior in terms of controlling the short-channel effects when compared to the conventional symmetrical double gate SOI MOSFET. We show that when the side gate length is equal to the main gate length, the device can be operated in an optimal condition in terms of threshold voltage roll-off and hot carrier effect. We further show that in the proposed structure the threshold voltage of the device is nearly independent of the side gate bias variation.

A New High Breakdown Voltage Lateral Schottky Collector Bipolar Transistor on SOI: Design and Analysis

Using two-dimensional process and device simulation, we present for the first time, a new high breakdown voltage two-zone base extended buried oxide (BOX) lateral Schottky Collector Bipolar Transistor (SCBT) on silicon-on-insulator with a breakdown voltage as high as 12 times that of the conventional lateral Schottky collector bipolar transistor. We have explained the new design features of the proposed Schottky collector structure and the reasons for its significantly improved breakdown performance. The proposed structure is expected to be suitable in the design of the new generation scaled high voltage Schottky collector bipolar transistors for low power high speed analog applications.

Simulation of trapping properties of high κ material as the charge storage layer for flash memory application

We investigated the trapping properties of high κ material as the charge storage layer in non-volatile flash memory devices using a two-dimensional device simulator, Medici. The high κ material is sandwiched between two silicon oxide layers, resulting in the Silicon-Oxide-High κ-Oxide-Silicon (SOHOS) structure. The trap energy levels of the bulk electron traps in high κ material were determined. The programming and erasing voltage and time using Fowler Nordheim tunneling were estimated by simulation. The effect of deep level traps on erasing was investigated. Also, the effect of bulk traps density, thickness of block oxide and thickness of high κ material on the threshold voltage of the device was simulated.

A compact nonquasi-static MOSFET model based on the equivalent nonlinear transmission line

A compact physics-based nonquasi-static (NQS) metal-oxide-semiconductor field-effect transistor (MOSFET) model with the equivalent nonlinear transmission line (TL) representing channel carriers drift-diffusion transport is developed and implemented in the simulation program with integrated circuit emphasis (SPICE) program. An auxiliary subcircuit is described, which efficiently solves the channel surface boundary potentials without the need for employing separate iterative algorithms. The short-channel effects and the quantum effects are efficiently included owning to a surface-potential-based modeling approach. In comparison with other Berkeley short-channel IGFET model 3 (BSIM3)-based NQS MOSFET models, it is shown that the new NQS TL model has the advantages in higher accuracy and substantially fewer number of model parameters. From comparison with a two-dimensional device simulator, it is demonstrated that the new NQS TL model can accurately predict dc, ac, and transient behavior of long- and short-channel n-type MOSFETs in all operational regions and for the input signal frequencies up to 10 f/sub T/ values, using only one set of model parameters.

Novel High-Density Low-Power Logic Circuit Techniques Using DG Devices

Novel high-density low-power double-gate circuit techniques for basic logic families such as NAND, NOR, and pass-gate are proposed. The technique exploits the independent front- and back-gate bias to reduce the number of transistors for implementing logic functions. The scheme substantially improves the standby and dynamic power consumptions by reducing the number of transistors and the chip area/size while improving the circuit performance. The power/performance advantages are analyzed/validated via mixed-mode two-dimensional MEDICI numerical device simulations, as well as by using physical delay equations.