Two-dimensional Device Simulation Research Articles

Impact Ionization Behavior in Bulk Fin Field Effect Transistors with Fin Body Width and Bias Conditions

The impact ionization behavior of bulk fin field effect transistors (FinFETs) was investigated with respect to fin body width (Wfin) and bias conditions. As fin width decreases to less than about 50 nm, the effect of parasitic source/drain series resistance becomes significant, resulting in a decrease in the impact ionization rate due to the increasing voltage drop across the resistance. We analyzed the ISUB/ID trend depending on the bias conditions (VGS=VDS and VGS=VDS/2) for devices with a Wfin thicker than 50 nm. Through two-dimensional device simulation, we showed the voltage drop and the peak electron temperature for various Wfin. It was also shown that the contact resistivity between the source/drain and the metal electrode is very important in the bulk FinFET with a very thin fin width.

Application of Double Gate Graded-Channel SOI in MOSFET-C Balanced Structures

This work studies the linearity of conventional and Graded- Channel (GC) Gate-All-Around (GAA) devices when applied in 2- MOS and 4-MOS balanced structures operating as tunable resistors. The study has been performed through device characterization and two-dimensional process and device simulations. Total harmonic distortion (THD) and third order harmonic distortion (HD3) have been evaluated. When taking into account similar on-resistance, the use of the GC GAA transistors in both 2-MOS and 4-MOS structures improves the linearity. The use of GC GAA devices in 2-MOS balanced structures allows a reduction of the gate overdrive voltage of 22.5% without degrading THD and HD3. On the other hand, the use of GC GAA devices in 4-MOS structures leads to an improvement in both HD3 and THD by 7 dB for devices with similar channel length at the same gate voltage overdrive.

Two-dimensional analytical Mott-Gurney law for a trap-filled solid

The letter presents a two-dimensional analytical model of the space charge limited (SCL) current injection in a solid with exponentially distributed trap energy state. By considering that the electrons are injected from an infinitely long emission strip of width W, the one-dimensional SCL current density is enhanced by a factor of 1+F(4∕π)∕(W∕L), where F=1∕(l+2) measures the mean position of the injected electrons in the solid of length L, and l is the ratio of the distribution of the traps to the free carriers. The analytical formula is verified by using a two-dimensional device simulator.

The study of δ-doped InGaP/InGaAs/GaAs pseudomorphic high electron mobility transistor

An enhancement-mode pseudomorphic high electron mobility transistor (E-mode pHEMT) with In 0.49Ga 0.51P/In 0.25Ga 0.75As/GaAs structure is studied in this paper. The two-dimensional device simulator, MEDICI, is used to solve the Poisson's equation and the electron/hole current continuity equations. An optimized δ-doped InGaP/InGaAs pHEMT structure is found to be superior to the conventional AlGaAs/InGaAs pHEMT. It reveals that the maximum drain-source current ( I DS) goes up to 1600 mA/mm and transconductance ( G m) is 2120 mS/mm.

Impact of Strain or Ge Content on the Threshold Voltage of Nanoscale Strained-Si/SiGe Bulk MOSFETs

The impact of strain on the threshold voltage of nanoscale strained-Si/SiGe MOSFETs is studied by developing a compact analytical model. Our model includes the effects of strain (Ge mole fraction in SiGe substrate), short-channel length, source/drain junction depths, substrate (body) doping, strained silicon thin-film thickness, gate work function, and other device parameters. The model correctly predicts a decrease in threshold voltage with increasing strain in the silicon thin film, i.e., with increasing Ge concentration in SiGe substrate. The accuracy of the results obtained using our analytical model is verified using two-dimensional device simulations.

Measurement of the hot carrier damage profile in LDMOS devices stressed at high drain voltage

In this paper, the hot carrier degradation of laterally diffused nMOSFETs is investigated in detail by the analysis of the fundamental device parameters and charge pumping measurements. Starting from this experimental characterization a new approach based on charge pumping technique is developed to estimate the spatial distribution of the hot carrier damage. This methodology has been applied on test structures, obtaining good results in the prediction of both the interface states and the trapped charges profiling. The supporting assumptions have been verified by fitting to the electrical data and by means of a two-dimensional device simulation.

Simulation and analysis of metamorphic high electron mobility transistors

In this paper, the metamorphic high electron mobility transistors (mHEMTs) are investigated numerically and compared with pseudo-morphic high electron mobility transistors (pHEMTs). The two-dimensional device simulator, MEDICI, is used to solve the Poisson's equation and the electron/hole current continuity equations. The influences of δ-doping concentration and position, gate width, spacer thickness, etc. on the performances of HEMTs are explored. It shows clearly that mHEMTs have higher transconductances, drain currents and DC voltage swings than pHEMTs.

A New Gate Induced Barrier Thin-Film Transistor (GIB-TFT) for Active Matrix Liquid Crystal Displays: Design and Performance Considerations

Reducing the OFF-state leakage current, and eliminating the pseudo-subthreshold conduction in polysilicon thin-film transistors (TFTs), is a major problem since the channel current is controlled by the potential barrier associated with the grain boundaries in the undoped channel. In this paper, we present for the time, a new gate-induced barrier TFT (GIB-TFT) in which the undoped channel has no grain boundaries, while the channel current is controlled by inducing large potential barriers in the channel. We demonstrate that the proposed GIB-TFT exhibits a steep subthreshold slope and at least three orders of magnitude less OFF-state leakage current when compared to the conventional polysilicon TFTs. Using two-dimensional and two-carrier device simulation, we have analyzed the various performance and design considerations of the GIB-TFT and explained the reasons for its improved performance

Current Collapse and High-Electric-Field Reliability of Unpassivated GaN/AlGaN/GaN HEMTs

Long-term ON-state and OFF-state high-electric-field stress results are presented for unpassivated GaN/AlGaN/GaN high-electron-mobility transistors on SiC substrates. Because of the thin GaN cap layer, devices show minimal current-collapse effects prior to high-electric-field stress, despite the fact that they are not passivated. This comes at the price of a relatively high gate-leakage current. Under the assumption that donor-like electron traps are present within the GaN cap, two-dimensional numerical device simulations provide an explanation for the influence of the GaN cap layer on current collapse and for the correlation between the latter and the gate-leakage current. Both ON-state and OFF-state stresses produce simultaneous current-collapse increase and gate-leakage-current decrease, which can be interpreted to be the result of gate-drain surface degradation and reduced gate electron injection. This study shows that although the thin GaN cap layer is effective in suppressing surface-related dispersion effects in virgin devices, it does not, per se, protect the device from high-electric-field degradation, and it should, to this aim, be adopted in conjunction with other technological solutions like surface passivation, prepassivation surface treatments, and/or field-plate gate

A collector-up heterojunction bipolar transistor using a p-type doping buried layer

In this paper, we report a collector-up npn heterojunction bipolar transistor (C-up HBT) which employs a p-type doping buried layer inserted between an extrinsic emitter and a subemitter for current confinement. Fabrication of C-up AlGaAs/GaAs HBTs with a selectively buried layer by metalorganic chemical vapour deposition (MOCVD) regrowth is described. The fabricated C-up AlGaAs/GaAs HBT demonstrates good common-emitter I–V characteristics and a current gain of 18. A systematic analysis is performed to verify the functionality of the p-type doping buried layer using a two-dimensional device simulator. It is found that the p-type doping buried layer should be biased properly to achieve the high efficiency of current confinement. And the HBT with a large ΔEV at the base-emitter heterojunction is preferred for the proposed C-up HBTs to reduce hole back-injection.

Implant-free high-mobility flatband MOSFET: principles of operation

Principles of operation of implant-free enhancement-mode MOSFETs (flatband MOSFET) are discussed. Epitaxial-layer structures designed for use in implant-free enhancement-mode devices and employing a high-kappa dielectric (kappacong20) and a strained InGaAs channel layer with a thickness of 10 nm have been manufactured on GaAs substrate. Proceeding from measured electron mobility mu as a function of the sheet-carrier concentration, enhancement-mode design considerations, saturation current IDss, and mobility requirements are discussed using two-dimensional device simulations. For the flatband MOSFET to compete successfully with other device designs, certain minimum channel mobilities are required. For RF applications, mu should exceed 5000 cm2/Vs while high-performance MOSFETs for digital applications may require even higher mobility for optimum operation. Finally, measured data of first 1-mum-GaAs-flatband enhancement-mode MOSFETs are presented; the saturation velocity of the InGaAs channel layer is derived; and measured IDss data are compared to the results obtained by simulations

A new grounded lamination gate (GLG) for diminished fringe-capacitance effects in high-/spl kappa/ gate-dielectric MOSFETs

A grounded lamination gate (GLG) structure for high-kappa gate-dielectric MOSFETs is proposed, with grounded metal plates in the spacer oxide region. Two-dimensional device simulations performed on the new structure demonstrate a significant improvement with respect to the threshold voltage roll-off with increasing gate-dielectric constant (due to parasitic internal fringe capacitance), keeping the equivalent oxide thickness same. A simple fabrication procedure for the GLG MOSFET is also presented

The Role of Residual Source/Drain Implant Damage Traps on SiC MESFET Drain I-V Characteristics

Experimental characterization of 4H-SiC power MESFETs with n + implanted source/drain ohmic contact regions, with and without a p-buffer layer, fabricated on semi-insulating (SI) substrates exhibited hysteresis (looping) in the drain I-V characteristics of both types of devices at 300K and 480K due to traps. However, thermal deep level transient spectroscopy (DLTS), thermal admittance spectroscopy (TAS), and thermal conductance spectroscopy could detect the traps only in the devices without buffer. Device simulation, using the two-dimensional device simulator Medici™, also showed hysteresis in both types of devices at 300K and 480K. Simulations suggest that, in addition to the SI substrate traps and surface traps, which are known to be a major cause of hysteresis in MESFET drain I-V characteristics, acceptor traps due to residual source/drain implant damage can also be a major contributor to the hysteresis. Further simulations suggest that much of the hysteresis at low gate voltages and all the hysteresis at high temperatures such as 480K are due to acceptor-type source/drain residual implant damage traps with energy levels distributed in the 4H-SiC band gap.

Analytical Modeling of Output Conductance in Long-Channel Halo-Doped MOSFETs

In this paper, a detailed physical analysis and an analytical derivation of the degradation of the output resistance (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">out</sub> ) observed in relatively long-channel laterally nonuniformly doped devices with halo implants are presented. Two-dimensional device simulations were performed, and the simulations show that the channel can be split into two uniformly doped transistors in series for the purpose of analysis. The lower doped bulk transistor is on the source side, while the higher doped halo transistor is toward the drain end. Based on this two-transistor analysis, a simple R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">out</sub> degradation model is derived for implementation in a MOSFET compact model

Anomalous Reduction of Hot-Carrier-Induced On-Resistance Degradation in n-Type DEMOS Transistors

Anomalous hot-carrier degradation phenomenon was observed in a 0.5-mum 12-V n-type drain-extended MOS transistors (N-DEMOS) with various n-type drain-drift (NDD) implant dosage. Under the same stress condition, the device with a higher NDD dosage produces a higher substrate current, a slightly higher transconductance degradation, but a lower ON-resistance (RON) degradation. Two degradation mechanisms are identified from the analysis of the electrical data and two-dimensional device simulations. The first mechanism is hot-electron injection in the accumulation region near the junction of the channel and accumulation regions. The second mechanism is hot-hole injection in the accumulation region near the spacer. This injection of hot holes creates a positive-charge trapping in the gate oxide, resulting in negative mirror charges in the accumulation region that reduces RON. The second mechanism is identified to account for the anomalous lower RON degradation

에피층 농도 변화에 따른 Multi-RESURF SOI LDMOSFET의 전기적 특성 분석

In this paper, we analyzed the breakdown voltage and on-resistance of the multi-RESURF SOI LDMOSFET as a function of epi-layer concentration. P-/n-epi layer thickness and doping concentration of the proposed structure are varied from <TEX>$2{\sim}5{\mu}m\;and\;1\{times}10^{15}/cm^{3}^{\sim}9\{times}10^{15}/cm^{3}$</TEX> to find optimum breakdown voltage and on-resistance of the proposed structure. The maximum breakdown voltage of the proposed structure is <TEX>$224\;V\;at\;R_{on}=0.2{\Omega}-mon^{2}\;with\;P_{epi}=3\{times}10^{15}/cm^{3},\;N_{epi}=7\{times}10^{15}/cm^{3}\;and\;L_{epi}=10{\mu}m$</TEX>. Characteristics of the device are verified by two-dimensional process simulator ATHENA and device simulator ATLAS.

Physics and Characterization of Various Hot-Carrier Degradation Modes in LDMOS by Using a Three-Region Charge-Pumping Technique

Degradation of lateral diffused MOS transistors in various hot-carrier stress modes is investigated. A novel three-region charge-pumping technique is proposed to characterize interface trap <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(N_ it)$</tex> and bulk oxide charge <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$Q_ ox$</tex> creation in the channel and in the drift regions separately. The growth rates of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$N_ it$</tex> and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$Q_ ox$</tex> are extracted from the proposed method. A two-dimensional numerical device simulation is performed to gain insight into device degradation characteristics in different stress conditions. This paper shows that a maximum <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$I_g$</tex> stress causes the largest drain current and subthreshold slope degradation because of both <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$N_ it$</tex> generation in the channel and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$Q_ ox$</tex> creation in the bird's beak region. The impact of oxide trap property and location on device electrical characteristics is analyzed from measurement and simulation.

Modeling of Body Factor and Subthreshold Swing in Bulk Metal Oxide Semiconductor Field Effect Transistors in Short-Channel Regime

A compact and empirical model of subthreshold swing S and body factor γ is developed in bulk metal oxide semiconductor field effect transistor (MOSFET) in the short-channel regime. Although the relation between S and γ is simply given as S=60(1+γ) in the long-channel regime, this relation no longer holds in the short-channel regime due to the short channel effect (SCE). The model is derived using the capacitance network model and by fitting analytical equations to two-dimensional device simulation results. It is confirmed that the model is valid not only at low drain voltage but also at high drain voltage considering the effect of drain-induced barrier lowering. This model is very effective in the design of variable threshold-voltage complementary metal oxide semiconductor (VTCMOS) circuits.

Microwave Class-F InGaP/GaAs HBT Power Amplifier Considering up to 7th-Order Higher Harmonic Frequencies

The first realization of a class-F InGaP/GaAs HBT amplifier considering up to 7th-order higher harmonic frequencies, operating at 1.9-GHz band, is described. A total number of open-circuited stubs for higher harmonic frequency treatment is successfully reduced without changing a class-F load circuit condition, using a low-cost and low-loss resin (tan δ = 0.0023) circuit board. In class-F amplifier design at microwave frequency ranges, not only increasing treated orders of higher harmonic frequencies for a class-F load circuit, but also decreasing parasitic capacitances of a transistor is important. Influence of a base-collector capacitance, C bc , for power added efficiency, PAE, and collector efficiency, η c , was investigated by using a two-dimensional device simulator and a harmonic balance simulator. Measured maximum PAE and η c reached 74.2% and 76.6%, respectively, using a fabricated class-F InGaP/GaAs HBT amplifier with collector doping density of 2 × 10 16 cm -3 . In case circuit losses were de-embedded for the experimental results, PAE and η c were estimated as 78.7% and 81.2%, respectively. These are very close to obtainable maximum PAE for the use of the InGaP/GaAs HBT.

BJT-based detector on high-resistivity silicon with integrated biasing structure

A novel method for biasing phototransistor-based radiation detectors on high-resistivity Si is presented, that relies on the integration into the detector base of a pnp transistor acting as a current source. The proposed approach can be extended in a natural way to the biasing of npn detector arrays, allowing different detectors to be biased at the same quiescent current, by connecting all the biasing pnp transistors with a diode-connected reference transistor (integrated onto the same chip), so that they form a current-mirror circuit. Relying on two-dimensional numerical device simulations, several test structures have been designed and fabricated, including single BJT detectors and detector arrays with pnp biasing transistors connected in the current-mirror configuration. The electrical characterization of fabricated structures shows that both single detectors and detector arrays are operational and behave in good agreement with simulations, thus demonstrating the feasibility of the proposed approach.