Two-dimensional Device Simulation Research Articles

Design of IGBT with integral freewheeling diode

A new power structure integrating a freewheeling diode in the termination region of a punch-through (PT) insulated gate bipolar transistor (IGBT) is presented. The proposed solution requires virtually no silicon area penalty with respect to a standard IGBT. Static and dynamic experimental results show the correct behavior of both IGBT and freewheeling diode. Further, it is shown that the lateral diode surrounding the multicellular IGBT can support IGBT direct current with low on-state voltage drop. The operation mechanisms of the composite structure and design techniques to improve structure dynamic behavior are investigated through two-dimensional numerical device simulations.

The effect of high-K gate dielectrics on deep submicrometer CMOS device and circuit performance

The potential impact of high permittivity gate dielectrics on device short channel and circuit performance is studied over a wide range of dielectric permittivities (K/sub gate/) using two-dimensional (2-D) device and Monte Carlo simulations. The gate-to-channel capacitance and parasitic fringe capacitances are extracted using a highly accurate three-dimensional (3-D) capacitance extractor. It is observed that there is a decrease in parasitic outer fringe capacitance and gate-to-channel capacitance in addition to an increase in internal fringe capacitance, when the conventional silicon dioxide is replaced by a high-K gate dielectric. The lower parasitic outer fringe capacitance is beneficial for the circuit performance, while the increase in internal fringe capacitance and the decrease in the gate-to-channel capacitance will degrade the short channel performance contributing to higher DIBL, drain leakage, and lower noise margin. It is shown that using low-K gate sidewalls with high-K gate insulators can decrease the fringing-induced barrier lowering. Also, from the circuit point of view, for the 70-nm technology generation, the presence of an optimum K/sub gate/ for different target subthreshold leakage currents has been identified.

Numerical analysis of bulk diffusion length in thin-film c-Si solar cells

Abstract We propose a novel technique of determining relationship between effective and bulk diffusion length of single-crystalline Si (c-Si) thin-film solar cells using two-dimensional device simulator. In addition, bulk diffusion length was obtained using the result of the simulation. Effective diffusion length was measured by LBIC method in order to presume bulk diffusion length of c-Si thin film. We obtained 6.7 μm for effective diffusion length of c-Si thin-film solar cell whose thickness was about 7 μm . We compared the result of measurement and simulation, bulk diffusion length of c-Si thin film prepared by CVD method was estimated more than 30 μm and recombination velocity was presumed 4 cm / s for front surface and 10 3 cm / s for rear surface of the cell.

Device simulation and modeling of microcrystalline silicon solar cells

Abstract Device modeling for p–i–n junction basis thin film microcrystalline Si solar cells has been examined with a simple model of columnar grain structure utilizing two-dimensional device simulator. The simulation results of solar cell characteristics show that open-circuit voltage ( V oc ) and fill factor considerably depend on structural parameters such as grain size and acceptor doping in intrinsic layer, while short-circuit current density ( J sc ) is comparatively stable by built-in electric field in the i-layer. It is also found that conversion efficiency of more than 16% could be expected with 1 μm grain size and well-passivated condition with 10 μm thick i-layer and optical confinement.

Analysis of thermal noise in scaled MOS devices and RF circuits

In this paper physics-based numerical simulation is applied to the evaluation of the noise performance of MOS devices and circuits for technologies with minimum feature size ranging from 0.25 to 0.1 μm. Adopting a simulation approach for noise calculations that considers the transistor as an active transmission line and by post-processing the results of two-dimensional hydrodynamic device simulations, a detailed analysis of the dependences of MOSFET noise parameters and minimum noise figure (NF) on bias and technology scaling is carried out. Furthermore, the impact of scaling on the performance of a simple low noise amplifier is analyzed; analytical models and physics-based device simulations provide predictions about the trend of NF and power consumption of the amplifier, for operation frequencies from 900 MHz up to 20 GHz. The results of this work confirm that noise performance improve as CMOS technology is scaled down, increasing the interest for CMOS low-noise amplifiers.

Side-Gate Design Optimization of 50 nm MOSFETs with Electrically Induced Source/Drain

50 nm metal oxide semiconductor field effect transistors (MOSFETs) with two poly-Si side-gates are designed. We discuss the device structure and its fabrication process. Then, we investigate the improvement in device performance focusing on short channel effect, current drivability and hot carrier effect with two-dimensional and two-carrier device simulation. The proposed fabrication method maintains compatibility with the conventional MOS technology. The simulation results reveal that when the side-gate length is equal to the main-gate length, the device can be operated in an optimal condition.

Analysis of one-sun monocrystalline rear-contacted silicon solar cells with efficiencies of 22.1%

21.4% efficient rear-contacted cells (RCC) with interdigitated contact grids processed at the Fraunhofer ISE on 1.25 Ω cm float-zone (FZ) silicon are analyzed in detail. The comprehensive description does not only include a two-dimensional numerical device simulation, but also a detailed analysis of the optical carrier generation using optical ray tracing and determination of the losses due to distributed metal resistance and perimeter currents employing circuit simulation. Bulk and surface recombination losses are separated, combining carrier lifetime and open-circuit voltage measurements with numerical device simulation. The interface surface recombination velocity of the thermally oxidized emitter covering the front surface is deduced to be 1500 cm/s and the bulk diffusion length within the 1.25 Ω cm FZ silicon base is 1200 μm. Despite this excellent bulk diffusion length, the simulations reveal that at a maximum power point 80% of the total recombination is due to Shockley–Read–Hall recombination in the base. It was determined that losses due to the distributed metal resistance within the contact grid (including nongeneration losses) caused an fill factor decrease of 1% absolute. Loss currents flowing out of the cell perimeter caused an additional fill factor loss of 1.5% absolute. It was predicted that changing the surface concentration of the front and rear emitter diffusion from 5×1018 to 1×1018 cm−3, while keeping the sheet resistance constant, effected a relative improvement of 3% in the efficiency of the RCC structure. In fact, this modification has lead to an increase in the realized cell efficiency from 21.4% to 22.1% (VOC=697.6 mV, JSC=39.8 mA/cm2, and FF=79.4%), i.e., a relative improvement of 3.3%. This cell has an efficiency of 18.6% (VOC=696.5 mV, JSC=33.9 mA/cm2, and FF=78.8%) if illuminated from the rear side.

Design curves of breakdown voltage at field plate edge and effect of interface charge

Useful design curves of breakdown voltage are provided, which allow determination of breakdown voltage at the field plate edge in terms of field plate length, oxide thickness, and substrate doping concentration. The effect of the interface charge on the breakdown voltage is analyzed and determined also from the curves. The analytical results show a fair agreement with the two-dimensional device simulations using MEDICI as well as with the experimental results reported.

Low Schottky barrier source/drain for advanced MOS architecture: device design and material considerations

An alternative MOSFET architecture based on the use of low barrier Schottky source/drain (S/D) contacts coupled to a thin silicon-on-insulator (SOI) film is described. Two-dimensional device simulations are used to demonstrate the advantage of low Schottky barrier S/D over conventional implanted technologies in terms of current drive capabilities. It is shown that the silicide penetration in the silicon does not increase the contact resistance for this structure while a severe degradation of the current drive is observed for conventional MOS architectures. Experiments conducted on Pt/Ge metallic stacks on p-type silicon show that very low Schottky barriers to hole can be obtained (∼50 meV).

Parasitic capacitance characteristics of deep submicrometre grooved gate MOSFETs

Grooved gate metal–oxide-semiconductor field-effect transistors (MOSFETs) are known to alleviate many of the short channel and hot carrier effects that arise when MOSFET devices are scaled down to very short channel lengths. However, they exhibit much higher parasitic capacitance with stronger bias dependence when compared to conventional planar devices. In this paper, we present a model for gate-to-drain and gate-to-source capacitance characteristics of a deep submicrometre grooved gate MOSFET. Both the intrinsic and extrinsic parts of the capacitance are modelled separately. In particular, the model presents a novel but simple way to account for the accumulation layer formation in the source/drain region of MOSFETs due to the application of the gate voltage. The results are compared with those obtained from a two-dimensional device simulator. The close match between the modelled and simulated data establishes the validity of the model. The model is then used to account for the superiority of capacitance characteristics of planar device structures and to arrive at optimization guidelines for grooved gate devices to match these characteristics.

A two-dimensional modeling of the fine-grained polycrystalline silicon thin-film solar cells

A two-dimensional device modeling for polycrystalline silicon thin-film solar cells was performed. A ThRee-dimensional Emitter Based on Locally Enhanced diffusion (TREBLE) concept was applied to evaluate the degree of leveling of the device efficiency. The model assumes a n +-p-p + junction device of a 3-μm grain size and 10-μm-thick polycrystalline Si columnar structure unit, where the n + regions extend along the grain boundaries. The analysis was carried out using ISE-DESSIS, a two-dimensional semiconductor device simulator. It has been found that open circuit voltage could be improved by increasing the base doping level to the optimum value of 10 17 cm −3. Preferential doping has a beneficial effect on short-circuit current of the cell and a slight influence on open circuit voltage. Conversion efficiency of ∼10% could be expected at the surface, recombination velocity of 10 4 cm/s and dopant diffusion depth along the grain boundary x gb=2.5 μm At base doping ∼10 17 cm −3 and well-passivated grain boundaries ( S gb=10 3 cm/s), an efficiency of approximately 12% may be obtained when x gb=3.7 μm.

Influence of polysilicon-gate depletion on the subthreshold behavior of submicron MOSFETs

Ion implantation, followed by annealing process, often leads to nonuniform doping and considerable depletion effect in the polysilicon gate of submicron MOS devices. Such an effect can alter notably the subthreshold characteristics and invalidate the conventional subthreshold current model. This paper studies the polysilicon-gate depletion effects on the subthreshold behavior based on results obtained from two-dimensional device simulation. An empirical expression is also suggested to describe the subthreshold current including the depletion effect.

Determining the onset frequency of nonquasistatic effects of the MOSFET in AC simulation

The frequency dependence of nonquasistatic (NQS) operation in MOS transistors is studied. With the help of a two-dimensional device simulator, a time varying sine function is applied to the gate at different frequencies. The inversion channel charge variation in response to the input signal at high frequency is compared with that at dc. By observing the frequency that generates an observable delay in channel charge response to the applied signal, the onset frequency of the NQS effect can be determined, which gives a limit to the valid quasistatic (QS) assumption. It was found that the onset frequency of the NQS effect is very close to f/sub T/, the unity gain frequency of a transistor, and the QS approximation is sufficient for most of the practical applications.

Study of radiation effects in /spl gamma/-ray irradiated power VDMOSFET by DCIV technique

Direct-current current-voltage (DCIV) measurement was used to monitor interface recombination currents in /sup 137/Cs /spl gamma/-ray irradiated commercial power VDMOSFETs. The data are correlated with the subthreshold I-V data and charge-pumping current data, which are obtained after various biased-annealing steps. The DCIV method is found to be a convenient technique in monitoring the radiation effects in power VDMOSFET devices. Various parameters measured with the DCIV technique are discussed in conjunction with the charge-pumping data and the data from the midgap method. A two-dimensional MOS device simulator, MINIMOS, was used to illustrate the DCIV data. The simulation results illustrate well the dependence of the measurable DCIV parameters on various radiation-induced physical parameters such as interface-trap density, fixed oxide charge density, and surface recombination velocity. A biased annealing experiment in nonirradiated virgin devices showed that the second current peak in the double peak structure of the DCIV data may be associated with the slow-frequency (300-6000 Hz) charge-pumping signal.

Optimum Designing of Single Crystalline Silicon Thin Film Solar Cells with Graded Active Layer

A carrier density gradient was given to the p-doped active layer of a conventional p–n junction solar cell employing the concept of the p–i–n junction structure used in amorphous silicon solar cells. Single crystalline silicon thin film solar cells with graded carrier density in the active layer were analyzed to optimize the cell structure utilizing a two-dimensional device simulator. Two types of cell structures were designed. In the case of Cell1, the carrier density was fixed to be 1016 cm-3 on the back surface field (BSF) side and changed exponentially for the p–n junction side from 1013 cm-3 to 1018 cm-3. On the other hand, in the case of Cell2, the carrier density was fixed to be 1016 cm-3 on the p–n junction side and changed exponentially for the BSF side from 1013 cm-3 to 1018 cm-3. Improvement in short circuit current density and open circuit voltage was observed. Therefore, high efficiency was expected under an electric field, considering the carrier density gradient. In the case of a solar cell with a 5-µm-thick solar grade single crystalline silicon film, a conversion efficiency of about 14% was obtained for a flat surface solar cell.

A critical review of thermal models for electro-thermal simulation

This paper discusses some limitations in the approaches commonly adopted for device and circuit electro-thermal simulation. Thermal models for circuit simulation assume a simple geometry for the region where power dissipation occurs. Available models are compared. The impact of model parameters and bias condition on simulation accuracy is discussed. A new approach for calculating the temperature distribution under both steady-state and transient conditions is also proposed. The accuracy of two-dimensional (2D) electro-thermal device simulations is then investigated. It is shown that 2D simulations can lead to markedly inaccurate results. Possible approaches to overcome these limitations are discussed.

Micro materials modeling in MINIMOS-NT

Considerable effort was spent on our two-dimensional device simulator MINIMOS-NT to get it ready for simulation of devices with high complexity in respect to materials, geometries, etc. Many of the existing physical models (band gap, mobility, thermal conductivity, energy relaxation times, specific heat, etc.) were refined, some of them were replaced by promising new ones, and many new models were added as well. Being an ancestor of the well-known MOS device simulator MINIMOS [1], its experience with Si devices was inherited. Thereby, MINIMOS-NT became a generic device simulator accounting for a variety of micro-materials, including group IV semiconductors, III-V compound semiconductors and their alloys, and non-ideal dielectrics.

MOSFET drain/source charge partition under nonquasi-static switching

The channel charge partition of metal-oxide-semiconductor transistors in nonquasi-static switching has been studied. A new approach, with the help of a two-dimensional device simulator is used to separate the direct current and transient current component during device switching. Unlike the commonly accepted 40/60 drain/source channel charge partition ratio, our results show that it is closer to the 0/100 as long as the switch speed is higher than the channel charging time. The result is important for pass-gate type circuits to evaluate the amount of charge transferred to the source and drain nodes.

Extraction of Trap States at the Oxide-Silicon Interface and Grain Boundary for Polycrystalline Silicon Thin-Film Transistors

A technique to extract trap states at the oxide-silicon interface and grain boundary has been developed for polycrystalline silicon thin-film transistors with large grains. From the capacitance–voltage characteristic, the oxide-silicon interface traps can be extracted. Potential and carrier density are also extracted. From the potential, carrier density, and current–voltage characteristic, the grain boundary traps can be extracted by considering the potential barrier at the grain boundary. Since these trap states are sequentially extracted, any shape of energy distribution of the trap states can be extracted. The correctness of this extraction technique is confirmed by comparison with two-dimensional device simulation.

Quantitative Investigation of Hot Carrier Induced Drain Current Degradation in Submicron Drain-Engineered Metal-Oxide-Semiconductor Field-Effect-Transistors

Parameters, such as the total amount of hot carrier induced interface states and substrate current, are not sufficient to evaluate hot carrier reliability in drain-engineered metal-oxide-semiconductor field-effect-transistors (MOSFETs). In this paper, for the first time, the distributions of hot carrier induced interface states are physically characterized and incorporated into two-dimensional device simulation to quantitatively study the structure-dependent drain current degradation in submicron MOSFETs, which give us insight into the relationship between degradation modes and device structures. The results show that the hot carrier induced series resistance effect in the sidewall spacer region plays an important role in drain-engineered MOSFETs. A different gate oxide thickness dependence of drain current degradation in thin gate oxide lightly-doped drain (LDD) MOSFETs is observed and is explained as the interface states enhanced series resistance effect in the LDD region.