TFET Research Articles

A novel nanosheet reconfigurable field effect transistor with dual-doped source/drain

—In this paper, a reconfigurable field-effect transistor (RFET) with dual-doped nanosheet architecture and triple independent gates is proposed and studied with the numerical simulations. The proposed RFET can behave as either an n/p-type MOSFET or an n/p-type tunneling-FET (TFET) according to different program biases. A comprehensive study is carried out on the device mechanism and the influence of key device parameters. Various metrics, such as the on-state current (ION), off-state current (IOFF), ION/IOFF, threshold voltage (VT) and sub-threshold swing (SS), are used to evaluate the proposed RFET. This RFET combining the advantages of the conventional MOSFETs (High ION and operation speed) and the new emerging TFETs (Low IOFF, sub-threshold swing and power dissipation) could make the circuit design more flexible and high efficiency, and improve the circuit performance.

Tunneling field-effect transistors with two-dimensional BiN as the channel semiconductor

The lack of suitable channel semiconductor materials has been a limiting factor in the development of tunneling field-effect transistor (TFET) architectures due to the stringent criteria of both air stability and excellent gate-tunable electronic properties. Here, we report the performance limits of sub-10-nm double-gated monolayer (ML) BiN TFETs by utilizing first-principles quantum-transport simulations. We find that ML BiN possesses an indirect bandgap of 0.8 eV and effective masses of 0.24m0 and 2.24m0 for electrons and holes, respectively. The n-type BiN TFETs exhibit better performance than the p-type ones, and the on-state current can well satisfy the requirements of the International Roadmap for Devices and Systems for both high-performance and low-power standards. Notably, we find that the BiN TFETs exhibit distinguished gate controllability with an ultra-low subthreshold swing below 60 mV/decade even with a small gate length of 6 nm, which is superior to the existing field-effect transistors, such as black phosphorus TFETs, GeSe TFETs, and BiN metal–oxide–semiconductor field-effect transistors. Furthermore, the BiN TFETs are endowed with the potential to realize high switching speed and low-power consumption applications because of their extremely short delay time and ultra-low power-delay product. Our results reveal that the ML BiN is a highly competitive channel material for the next-generation TFETs.

TCAD simulation study of heavy ion radiation effects on hetero junctionless tunnel field effect transistor

Semiconductor devices used in radiation environment are more prone to degradation in device performance. Junctionless Tunnel Field Effect Transistor (JLTFET) is one of the most potential candidates which overcomes the short channel effects and fabrication difficulties. In this work, 20 nm JLTFET is proposed with Silicon in the drain/channel region whereas source uses different materials, Silicon Germanium (SiGe), Gallium Nitride (GaN), Gallium Arsenide (GaAs), Indium Arsenide (InAs). The device performance is examined by subjecting it to heavy ion radiation at a lower and higher dose of linear energy transfer (LET) values. It can be seen that the most sensitive location is the source/channel (S/C) interface for SiGe, GaN and GaAs whereas the drain/channel (D/C) interface for InAs. Further analysis is carried out at these vulnerable regions by matching ION of all materials. The parameters, transient peak current (Ipeak), collected charge (QC), threshold voltage shift (ΔVth) and bipolar gain (β) are extracted using transient simulations. It is observed that for a lower dose of LET, Ipeak of SiGe is 27% lesser than InAs and for higher dose of LET, SiGe shows 56% lesser Ipeak than InAs. SiGe is less sensitive at lower and higher dose of LET due to reduced ΔVth, tunneling and electron density.

Source engineered TFET for digital inverters application

This article delves into a performance evaluation of source engineered asymmetric Tunnel Field Effect Transistors using Sentaurus TCAD. The focus of this analysis centers around Single and Double gate extended Source TFET (SG-ESTFET and DG-ESTFET) device configurations. The study emphasizes the reliability of these devices for circuit applications taking in account interface trap charges. Various digital inverters based on the aforementioned TFET devices are designed, showcasing their potential utility in terms of different delay parameters. Additionally, the article explores transient characteristics and notes the occurrence of undershoot when interface trap charges are present at oxide-semiconductor interfaces. Notably, the findings indicate that DG-ESTFET surpasses SG-ESTFET in mitigating undershoot, and the measured propagation delay is reported to be 9 ps.

Frequency doubler utilizing hetero gate dielectric tunnel field-effect transistor

With the rapid advancements in wireless communication and high-density integrated circuits, the demand for high-frequency sources has become paramount for transmitting vast amounts of information. Modern communication systems often utilize low-frequency sources at the transmitting end, converting them into high-frequency carriers through Intermediate Frequency (IF) for transmission to the receiving end. However, challenges arise in stabilizing high-frequency Voltage Controlled Oscillators (VCOs), leading to the necessity of Frequency Multipliers (FMs) in high-frequency circuits. While existing FMs face issues like harmonic distortion due to internal nonlinear devices, this paper proposes a single-device Frequency Doubler (FD) operation using Hetero-Gate Tunnel Field Effect Transistor (HG-TFET) with ambipolar characteristics. HG-TFET integrates high-κ (HK) materials and an HG structure in the gate dielectric, achieving independent control of tunneling distances and synchronous operation of source-to-channel and channel-to-drain tunneling currents (I SC and I CD) to facilitate FD operation. The paper presents the HG-TFET structure, process flow, and simulation models, followed by an exploration of its operating mechanism and characteristics. The FD circuit configuration, operational principles, and conditions for normal operation are detailed, emphasizing the importance of aligning I SC and I CD. The impact of adjusting HK lengths on I SC and I CD is analyzed, demonstrating the ability to independently control these currents through HG-TFET. Simulation results for FD operation under varying HK lengths (1–10 nm) validate the proposed approach. Additionally, the paper investigates the influence of dielectric constant (10–32) and gate dielectric thickness (2–5 nm) on FD performance, highlighting the potential for further optimization. In conclusion, this study establishes a foundation for normal FD operation through the symmetrical control of ambipolar and on currents using HG-TFET. The proposed structure and techniques open avenues for improving the efficiency and reliability of frequency-doubling applications in high-frequency circuits.

Joint Mechanism (Tunneling and Thermionic Emission) for Improved Performance of a Dielectric Modulated Transistor Biosensor

The manuscript deals with a novel biosensor structure and reports the effects of including thermionic emission in an electrically doped Tunnel FET. It comprises a comparative analysis between two biosensors based on a pure tunnelling transistor and a transistor which combines the tunnelling and thermionic emission carrier transport in the same device. The manuscript first discusses the physics of Tunnel FET when vertical thermionic emission is included with horizontal tunnelling through an additional electron source (AES). Subsequently, the biosensor is designed using the combined mechanism structure a comparative analysis of biosensors is done in terms of various DC and RF parameters for different biomolecules of proteins. Moreover, workfunction engineering is implemented to the combined mechanism biosensor and sensitivity is analyzed by drain current and transconductance.

Design and Performance Assessment of a Label- free Biosensor utilizing a Novel TFET Configuration

The present study presents an innovative idea: an original design for a label-free biosensor utilizing H-shape channel configuration within a dielectrically modulated (DM) double-gate TFET (DGTFET) framework, which includes the incorporation of a drain pocket (DP). This design concept is introduced In this study, an analytical model for the DM DPDG-TFET has been created for the first time was formulated and subsequently verified through comparison with industry-standard simulation software (Silvaco TCAD). In this paper we have examine both the biosensor's sensitivity and its effectiveness when employed as a tunnel field-effect transistor (TFET) device. A comprehensive analysis of the device's performance has been conducted. The innovative configuration of the suggested TFET results in heightened sensitivity. Incorporating a drain pocket (DP) at the junction between the drain and channel effectively eliminates ambipolarity, showcasing a successful approach. The H-shape DM DPDGTFET design demonstrates its superiority over various devices documented in the literature. The presence or lack of electric charge in various biomolecules is examined in order to evaluate the device's sensitivity as a label-free biosensor.

Robust type-III C3N/Ga2O3 van der Waals heterostructures

By combining two-dimensional (2D) materials with different band alignments at the contact interface, van der Waals heterostructures (vdWHs) can achieve multifunctional device applications. Here, through first principles methods, we constructed two C3N/Ga2O3 vdWHs named P↑ and P↓ because of the intrinsic polarization of Ga2O3 to study electronic, interfacial and optical characteristics. We find that the P↑ and P↓ both display a unique kind of band alignment known as broken-gap or type-III. This feature makes them highly suitable for tunnel field effect transistors (TFETs) applications. To the best of our knowledge, the tunnel window of the P↓ is the largest among the theoretical studies, reaching 0.993 eV. The electronic structure and band edge alignment of the C3N/Ga2O3 vdWHs show a weak dependence on strain engineering or external electric field. Normal-to-plane compressive strains effectively enhance the tunneling probability. We can acquire essential insights into this novel material system and its promise for future TFETs by analyzing the electrical characteristics of the C3N/Ga2O3 vdWHs.

Investigation of spacer-engineered stacked nanosheet tunnel FET with varying design attributes

The stacked nanosheet field-effect transistors (SNS-FETs) are potential contenders for sub-7 nm technology. Device miniaturization leads to a larger off-state current and a higher subthreshold slope in SNS-FETs. Unlike SNS-FETs, the stacked nanosheet tunnelling field effect transistors (SNS-TFETs) function as switches in integrated circuits, featuring high performance and low power consumption. The endeavour aims to investigate how each design parameter optimises the switching characteristics of the SNS-TFET device. This paper examines various design attributes, such as different dielectric spacer materials, nanosheet width (NW), nanosheet thickness (NT), source doping, drain doping, etc. The Cogenda Visual TCAD serves as a tool for conducting device simulations. According to the simulation study, the use of a high-k hafnium dioxide (HfO2) spacer produces a higher switching ratio ( 7.28×1011 ) and a lower subthreshold swing (20.303 mV/decade). Using either low-k or no spacers reduces the overall gate capacitance and unit frequency gain compared to high-k spacers. Upscaling the nanosheet width (10 to 50 nm) enhances the switching ratio by 1.11×101 and transconductance by 61.92%. Downscaling the nanosheet thickness (6 to 4 nm) at the optimized nanosheet width (50 nm) improves the switching ratio by 1.88. Increasing the gate length from 8 to 16 nm reduces the leakage current by 2.34×10−2 A and improves the switching ratio by 2.90×101. An increase in the source doping level from 1×1020 to 5×1020 cm−3 results in a 1.07×102 decrease in the switching ratio and a 2.48-fold increase in the subthreshold swing. Furthermore, the findings indicate that drain doping is crucial in determining ambipolar current. In SNS-TFET, ambipolar current reduces significantly when drain doping is 1×1017 cm−3. Thus, the proposed work addresses the limitations of scaling and optimised design parameter characteristics for low-power nanoscale circuits.

Insights into the design principles of JF-ED-VTFET for biosensing application

In this research article, we have designed a junction-free electrostatically doped vertical tunnel field-effect transistor (JF-ED-VTEFT) for label-free biosensing applications. We incorporated a nano-cavity within the gate-oxide layer near the source end of the FET to enable the detection of biomolecules based on the principle of dielectric modulation and without the requirement of external labeling. The proposed biosensor is thoroughly analyzed, considering various aspects such as electric field, energy band, transfer characteristics, and sensitivity parameters including energy band diagram, ON-current, ION/IOFF ratio, electrical analysis, and surface potential characteristics. The investigation of sensitivity encompasses practical challenges, such as different filling factors and step-profiles resulting from steric hindrance. In addition, the performance of the biosensor is evaluated by analyzing the temperature and scaling fluctuation in the integrated nanocavities. Additionally, values of biomolecules that are close to standard have been taken to validate the performance and provide insight into the sensitivity of the biosensor for detecting and analyzing the molecules.

Electrical characterization of multi-gated WSe2/MoS2 van der Waals heterojunctions

Vertical stacking of different two-dimensional (2D) materials into van der Waals heterostructures exploits the properties of individual materials as well as their interlayer coupling, thereby exhibiting unique electrical and optical properties. Here, we study and investigate a system consisting entirely of different 2D materials for the implementation of electronic devices that are based on quantum mechanical band-to-band tunneling transport such as tunnel diodes and tunnel field-effect transistors. We fabricated and characterized van der Waals heterojunctions based on semiconducting layers of WSe2 and MoS2 by employing different gate configurations to analyze the transport properties of the junction. We found that the device dielectric environment is crucial for achieving tunneling transport across the heterojunction by replacing thick oxide dielectrics with thin layers of hexagonal-boronnitride. With the help of additional top gates implemented in different regions of our heterojunction device, it was seen that the tunneling properties as well as the Schottky barriers at the contact interfaces could be tuned efficiently by using layers of graphene as an intermediate contact material.

Robustness of Raised Buried Oxide Ferro Electric Tunnel FET in presence of Temperature and Traps and its Analog/RF Performance

Robustness of Raised Buried Oxide Ferro Electric Tunnel FET in presence of Temperature and Traps and its Analog/RF Performance

Design and application of germanium based complementary TFET devices with step tunneling paths

Expanding tunneling has consistently been one of the approaches to enhance the on-state current (Ion) and performance of Tunnel Field-Effect Transistor (TFET). This paper proposes a novel structure for TFET called Step Tunneling Path TFET (STP TFET). The stepped tunneling path is achieved by preparing majority carrier channel and introducing pocket doping layers and lightly doped channel extension regions in the channel. Taking Germanium TFET as an example, the complementary structures, electrical parameters, DC and analog characteristics of STP TFET are investigated. Simulation results demonstrate that, compared to normal TFET, STP TFET exhibits significant improvements in Ion (n-TFET∼18/p-TFET∼45 times), cut-off frequency (n-TFET∼6/p-TFET∼16 times), Gain Bandwidth Product enhancement (n-TFET∼22/p-TFET∼16 times), and Transconductance Frequency Product enhancement (n-TFET∼3/p-TFET∼15 times). Furthermore, in the C-TFET inverter, the transient rise and fall times have decreased by 149 and 199 ns, respectively, while the voltage gain has increased by 6.7 times. The proposed device shows promising potential for applications in high-speed and low-power circuit designs.

2-D Si0.8Ge0.2 source double-gate pocket PTFET for low power application: Modeling and simulation

To process 1-bit of information the small supply voltage (Vdd) and minimal leakage current are needed for transistors. Subthreshold swing (SS) of 60 mV/dec at 300 K is the basic bottleneck in metal oxide semiconductor field effect transistors. DFT in QuantumATK R-2020.09 was used to study Si0.8Ge0.2 band structure and band gap. A p-type tunnel field effect transistor (PTFET) was modeled employing the dual gate concept. Top gate has two metals; source and counter doped pocket are Si0.8Ge0.2. According to the proposed device simulation, the proposed device is showing excellent thermal stability for large on-current (Ion), weak off-current (Ioff), and weak ambipolar current (Iambi) at different temperatures. The proposed device achieves the Ion of 72.44 µA/µm and 3.2 µA/µm at supply voltage of −1 V and −0.5 V, respectively. At −0.5 V of Vdd, current ratio of Ion/Ioff is more than 1012, so device can be used for low power applications.

GaAsSb/InGaAs tunnel FETs using thick SiO2 mask for regrowth

The regrowth conditions for lateral tunnel FETs featuring heterojunctions involve a tradeoff between selective growth and heavy doping. This study mitigated the connection between single crystals on the InP layer and polycrystals on the SiO2 mask by significantly increasing the thickness of the SiO2 mask to surpass that of the growing GaAsSb layer. We successfully fabricated p-GaAsSb/i-InGaAs tunnel FETs using a thick SiO2 mask, wherein the carrier concentration of the p-GaAsSb source was 5 × 1019 cm−3, and the growth temperature was maintained at 500 °C. The observed current–voltage (I–V) characteristics exhibited an on/off ratio of 5 × 104 and demonstrated ambipolar current behavior, confirming the presence of a p-type source. However, the observed subthreshold swing (SS) was limited to 120 mV dec−1. In comparison with the I–V characteristics of the planar transistor, degradation of SS can be explained by interface state, and the factor that characterizes the change of the drain current with the surface potential dΨs/d(log10ID) is estimated as 52 mV dec−1.

Dielectrically modulated hetero‐material double gate tunnel field‐effect transistor for label free biosensing

AbstractThis work proposes a novel double gate hetero‐material tunnel field effect transistor for label free biosensing applications. The device consists of III‐V semiconductor gallium arsenide (GaAs) which serves as a substrate. Source and drain regions made of Germanium are used due to its compatibility with GaAs. Cavities of 15 × 1.5 nm are created near source‐channel junctions for the biomolecules to be placed in. The ION sensitivity of 2.23 × 106 for neutral biomolecules has been obtained from 2D simulations using ATLAS TCAD software. Furthermore, transconductance sensitivity of 2.27 × 106, ION/IOFF sensitivity of 2.46 × 105, subthreshold swing (SS) sensitivity of 28.6 mV/decade and threshold voltage sensitivity of 1.2 mV for neutral biomolecules is obtained. The ION sensitivity of 3.93 × 106 and 1.42 × 106 for positively and negatively charged biomolecules respectively has been obtained. Also, SS sensitivity of 28.3 and 28.8 mV/decade for positively and negatively charged biomolecules respectively has been observed. ION sensitivity shows that the proposed device is 1000× better than the conventional one.

Assessment of temperature and ITCs on single gate L-shaped tunnel FET for low power high frequency application

In a vertical TFET structure, controllability over the gate is enhanced because of the favorable electrostatic potential and tunneling under the entire gate region by preventing the direct source to drain tunneling. For an L-shaped TFET, the Band-to-Band-Tunneling (BTBT) is perpendicular and parallel to the channel length. Also, it has a higher I on (ON-current) with suppressed ambipolar current (low I ambi ) and is more scalable than other vertical BTBT mechanism-based TFET structures. The reliability of n-type single gate L-shaped TFET (SG-nLTFET) is investigated by examining: (1) impact of temperature (Temp K ) variation (from 260 K to 460 K) and (2) Interface trap charge (ITCs) polarity at fixed charge density on analog /RF /linearity figure of merits (FOMs). The obtained results reveal that change in polarity of ITCs at the Si/HfO 2 interface,modifies the analogue characteristics of the SG-nLTFET significantly in terms of turn-on voltage as well as I on . The temperature sensitivity of SG-nLTFET device indicates that the ShockleyReadHall (SRH) and Trap-Assisted-Tunneling (TAT) phenomenon dominates at lower gate bias and degrades the I on /I off ratio at high temperatures. On the other hand, the BTBT mechanism predominates in the subthreshold regime of transfer characteristics. Furthermore, the results reveal that the off-state current (I off ) degrades dramatically at high temperatures. According to the empirical analysis, SG-nLTFET is insusceptible to Positive-ITCs (Donor trap charges, P-ITCs) present at Si/HfO 2 interface in comparison to Negative-ITCs (Acceptor trap charges, N-ITCs).

Thin-body effects in double-gate tunnel field-effect transistors

Scaling down the body thickness (T b) of double-gate tunnel field-effect transistors (DG-TFETs) is helpful in suppressing short-channel effects, but it may give rise to thin-body effects (TBEs). Based on 2D device simulations, this study examines the mechanisms and influences of TBEs in DG-TFETs as T b is scaled down. Differently from previous beliefs, the on-current degradation in thin-body DG-TFETs is not mainly caused by the volume effect, but rather by a newly defined TBE named lateralization effect. This is because the lateralization of tunneling direction significantly increases tunnel width, whereas the reduction of tunneling volume is quite limited due to narrow tunneling regions. To study the T b-dependence of current, therefore, the vertical tunneling has to be taken into consideration. When considered as a TBE, the fringing field effect caused by reduction in T b is not significant in degrading the on-current of thin-body DG-TFETs because the narrow tunneling regions are strongly gate-controlled. The only TBE that enhances the on-current is the coupling effect, but its role is only significant for low-bandgap bodies in which the coupling effect can efficiently promote the tunneling towards the body center. Not as previously thought that the quantum confinement effect monotonically increased, it even decreases as T b decreases down to sub-10 nm before turning to increase, thanks to the space sharing between proximate local quantum wells. A comprehensive understanding of the TBEs is useful for providing design insight, especially for determining the optimal T b to maximize the on-current.

Design and implementation of the logic gates using electrically doped configurable polarity control double gate tunnel FET

This paper designs and implements the basic logic and universal gates based on the proposed electrically doped, configurable polarity control double gate tunnel FET (ED-CPC-DGTFET). In contrast to the CMOS and MOSFET, the primary concern of the proposed device is to overcome the transistor count needed to design logic gates. A few compact realizations of logic gates have been reported earlier using conventional double-gate TFETs. The main key to designing and implementing logic gates with the proposed structure is controlling the channel’s tunneling barrier height by altering the gate electrode work function. Additionally, abrupt interband tunneling of TFET by varying gate bias makes the device appropriate for implementing logic gates. The proposed device has a dynamic configuration that can change from n-type to p-type DGTFET by varying the bias at PG-1 and PG-2. Since lightly doped TFETs have a low ON-state current therefore, a high-k material (HfO 2 ) is employed in place of SiO 2 on top of the source side to enhance the ON-state current. Using two-dimensional simulations, the device is designed to implement logic gates with gate lengths of 50 nm and silicon body thicknesses of 10 nm (t si ). OR and AND logic gates are implemented using the n-type ED-CPC-DGTFET structure, and universal gates are implemented using the p-type variant of the proposed ED-CPC-DGTFET structure by independently biasing the top and bottom gates against various inputs.

A bio-inspired ferroelectric tunnel FET-based spiking neuron for high-speed energy efficient neuromorphic computing

In this study, a novel spiking neuron based on double-gate ferroelectric tunnel field effect transistor (DG-FE-TFET) is proposed in the 50 nm technology node. Through calibrated simulations in Atlas TCAD, it is verified that by leveraging the forward transfer characteristics, the device accurately emulates the spiking patterns exhibited by biological neurons. The device works on tunneling mechanism which ensures low voltage operation and thereby reduces overall energy consumption. The proposed neuron consumes an energy of 0.58 aJ per spike, which is 1.29, 41.38, 7.75 × 105, 12.9 × 105, 1.89 × 105, 13.79 × 106, and 7.75 × 107 times lesser than V-DGTFET, FE-JLFET, Z2-FET, DG-TFET, FD-MOSFET, Ge-MOSFET, and Si-MOSFET. Notably, the neuron operates without the need for additional reset circuitry and achieves spiking frequency of 344 GHz, which can be attributed to the sharp switching characteristics of the proposed device. This greatly simplifies implementation and facilitates a higher neuron density for energy-efficient neuromorphic chips with high-speed capabilities. Finally, based upon the proposed neuron, a multi-layer spiking neural network (SNN) is designed in Python platform. The network is implemented for signal classification with an accuracy of 84.4%.