Trigger Current Research Articles

Analysis of the electrical characteristics of SCR-based ESD Protection Device (PTSCR) in 0.13/0.18/0.35um process technology

In this paper, an experimental analysis of the electrical characteristics of the PTSCR was conducted. The PTSCR contains a high trigger current and a holding voltage that enables latch-up immune during normal operation. The PTSCR in each process technology is verified by the TLP system as well as a hot chuck controller. The experimental results show that the trigger current and holding voltage are higher than that of other SCR devices. At higher temperatures, the holding voltage of the PTSCR decreased due to the operation mechanism of the SCR, while the trigger current increased due to the MOSFET trigger mechanism.

A 12-kV High-Voltage Semiconductor Switch Based on 76-mm Reverse-Switching Dynistors

This paper describes the construction and experimental tests of a 12-kV high-voltage high-action generator based on reverse-switching dynistor (RSD) assembly. The main RSD unit consists of seven 76-mm-diameter dynistor pieces connected in series with a blocking voltage of about 2.4 kV, a magnetic switch based on a 1K101 amorphous alloy core, the trigger system based on a saturable transformer, and a 16-mm RSD assembly; the trigger current could reach 2 kA in amplitude with 1-μs duration under 10 kV. The working voltage rate of this RSD unit is about 8-12 kV. Experiment on a 2.2-mF capacitor test bed under 12 kV working voltage, the switch current amplitude reached 150 kA with 300-μs duration; the transferred charge is about 26.5 C and the action is 2.94 MA <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> s, respectively.

A Scalable SCR Compact Model for ESD Circuit Simulation

A scalable compact model for SCR-based electrostatic discharge (ESD) protection devices is presented. This model captures the effect that layout spacing has on SCR characteristics, such as holding voltage and trigger current. The model also captures both the delayed turn-on of the SCR, which results in large voltage overshoots during fast rise-time ESD events and the charge removal mechanisms that underlie the turn-off transient. Bias and time dependences of SCR on-resistance are captured with a resistance model that accounts for self-heating.

Experimental and Theoretical Analyses of the Electrical SOA of Rugged p-Channel LDMOS

Numerical TCAD and transmission line pulse analysis of an electrical safe operating area of a robust p-channel lateral DMOS transistor is performed. The observed independence of the trigger current on the applied gate-source voltage is attributed to a lack of quasi-saturation effect which is usually observed in an n-channel LDMOS. The dependence of the trigger voltage on the length of channel and drift regions is also analyzed, and the tradeoff with the specific on-resistance (RDSon) is given.

Simulation and modelling of VDMOSFET self protection under TLP-stress

Abstract We present a simple and practical model for modelling the electrical behaviour of scalable vertical diffused MOSFETs (VDMOSFETs) under TLP stress. The trigger current is found to be dependent from gate–source voltage and geometry. A scalable model for analog circuit simulation is developed. As application example, self protection of VDMOS in resistive coupled gate configuration is investigated. For this purpose the device behaviour under TLP stress is modelled. The model is shown to predict VDMOS self protection under TLP stress for a wide range of geometries in an excellent way. A comprehensive analytical model calculation is added which explains the range of model validity. Within this range maximum HBM rating of the resistive gate coupled devices is predicted correctly.

Avalanche Breakdown Delay in High-Voltage p-n Junctions Caused by Pre-Pulse Voltage From IEC 61000-4-2 ESD Generators

Electrostatic-discharge (ESD) tests with IEC 61000-4-2 generators are often performed at component level but are known to suffer from poor reproducibility. In this paper, it is shown that IEC 61000-4-2 generators can charge the tested device to several tens of volts before the actual ESD pulse is applied. This pre-pulse voltage (PPV) can lead to delayed avalanche breakdown (BD) initiation in silicon junctions. The origin of the BD delay is the emptying of deep trap states within the space-charge region, which lowers the contribution to the generation current due to carrier emission from the deep states. The BD delay is critical for ESD protection devices and can also lead to a dramatic reduction of the snapback trigger current in DMOS transistors. However, transient gate turn-on of the DMOS transistor eliminates the BD delay and can thus increase the ESD robustness. It is shown that the PPV varies strongly between commercial IEC generators, and it is proposed that this could be one of the main reasons for the poor reproducibility of IEC tests. A newly proposed method to deliver an IEC 61000-4-2-shaped pulse through a 50-¿ transmission line is investigated with respect to the correlation with real IEC generators. It is shown that PPV-related issues are not addressed by this method, unless an additional bias voltage is applied during the test. It is also demonstrated that PPV is existent in real-world IEC discharges and must not be neglected for component qualification.

Plasma Stability in a Triggered Vacuum Switch

A triggered vacuum switch (TVS) has found fast growing applications in the fields of pulse power system. However, its popularization is still limited due to the trigger stability and accuracy. Research on the trigger process of TVS is one of valid ways to enhance the TVS performances. A sample of TVS was fabricated in this paper. An LC test circuit of two groups of parameters was set up. The trigger pulse parameters were adjustable, and trigger processes were stored by digital oscilloscope and high-speed camera, respectively. Experimental tests were made in three different kinds of trigger power according to the numerical degree. The different trigger power leads to different initial plasmas, i.e., sufficient initial plasma, insufficient initial plasma, and the transition stage between them. The trigger process and its stability are discussed based on the waveforms and photographs. Field emission causes the point discharge of trigger pin and leads to the primary stage of initial plasma. The development of initial plasma is analyzed by theoretical analysis and experimental data. The results show that sufficient initial plasma is a prerequisite for the stability of turning-on TVS, while insufficient initial plasma leads to chopping both in trigger current and voltage when triggering TVS. Sufficient initial plasma can also promote the trigger lifetime and accuracy, with a trigger delay limited in hundreds of nanoseconds.

Design of SCR-based ESD protection device for power clamp using deep-submicron CMOS technology

The proposed device has a high holding voltage and a high triggering current characteristic. These characteristics enable latch-up immune normal operation as well as superior full chip electro-static-discharge (ESD) protection. The device has a small area in requirement robustness in comparison to gate-grounded NMOS (ggNMOS). The proposed ESD protection device is designed in 0.25μm CMOS technology. In the experimental result, the proposed ESD clamp has a double trigger characteristic, a high holding voltage of 3.8V and a high trigger current of greater than 120mA. The robustness has measured to HBM 8kV (HBM: human body model) and MM 400V (MM: machine model). The proposed device has a high-level It2 of 52mA/μm approximately.

Design of SCR-Based ESD Protection Device for Power Clamp Using Deep-Submicron CMOS Technology

The novel SCR-based (silicon controlled rectifier) device for ESD power clamp is presented in this paper. The proposed device has a high holding voltage and a high triggering current characteristic. These characteristics enable latch-up immune normal operation as well as superior full chip ESD protection. The device has a small area in requirement robustness in comparison to ggNMOS (gate grounded NMOS). The proposed ESD protection device is designed in 0.25μm and 0.5μm CMOS Technology. In the experimental result, the proposed ESD clamp has a double trigger characteristic, a high holding voltage of 4V and a high trigger current of above 350mA. The robustness has measured to HBM 8kV (HBM: Human Body Model) and MM 400V (MM: Machine Model). The proposed device has a high level It2 of 52mA/μm approximately.

Electrothermal Characteristics of Strained-Si MOSFETs in High-Current Operation

The electrothermal characteristics of strained-Si MOSFETs, operating in the high-current regime, have been studied using device simulation. The phonon mean-free-path of strained-Si devices in the presence of high electric fields is determined, based on fullband Monte Carlo device simulation. Strained-Si nMOS devices have higher bipolar current gain and impact ionization rates compared to bulk-Si nMOS devices due to the smaller energy bandgap and longer phonon mean-free-path. Even though strained-Si devices have self-heating problems due to the lower thermal conductivity of the buried SiGe layer, the devices can be used beneficially for electrostatic discharge protection devices to achieve lower holding voltage (V/sub h/) and higher second breakdown triggering current (I/sub t2/), compared to those of bulk-Si devices, owing to the high bipolar current gain and current uniformity.

The Impact of CMOS technology scaling on MOSFETs second breakdown: Evaluation of ESD robustness

The impact of CMOS technology scaling on the second breakdown of ESD protection devices has been investigated using 2-D simulations and analytical calculations. It is shown that the second breakdown trigger current (It 2 ) can not be reliably used as an ESD robustness criterion in sub-0.18 um ESD protection devices. When a technology feature size is reduced, the doping of drain and drain extension regions is significantly increased. Thus, the ESD device failure due to the self-heating effect occurs without the second snapback region in high current I-V curve and It 2 current can not be properly extracted. Instead of It 2 current criterion, we propose to use the maximum failure temperature criterion.

Partial discharge testing of solder fillets on PCBs in a partial vacuum: new experimental results

This work investigates the influence on the partial discharge (PD) onset due to the geometry of solder fillets of aerospace and spacecraft component assemblies operating in vacuum and at high voltages. An automatic measuring system has been developed and calibrated to detect PD signals in vacuum (proportional to the apparent charge) which are recorded and displayed in terms of amplitude and temporal distributions. The experimental part of the project is aimed at investigating the influence of the geometry of solder fillets (produced according to the European space industry standard, ECSS-Q-70-08), on the occurrence of PD activity. Stranded terminals of high voltage cables were soldered to circular copper pads on FR4 fiberglass epoxy printed circuit board (PCB). Various copper electrode configurations have been produced and, prior to the test program, they were characterized for dimensional, electrical and optical properties. Two types of solder fillet geometries have been realized for each electrode configuration: round joints with an abundance of solder and sharp pointed joints made with minimal solder. The minimum distance between electrodes for all samples is nominally 5 mm. Paschen-like curves were established from measurements performed where the product of pressure x distance lies in the range of 2 mbar mm-50 mbar mm. Corona inception voltage (CIV) and corona extinction voltage (CEV) values were recorded at different values of pressure x distance. Stable glow discharge triggering voltage and current were also measured. The experimental results indicated that the PD activity for the sharp pointed pads and sharp pointed joints is greater than the other cases, but no significant differences (less than 50 V) of the values of CIV and CEV have been found.

Improved high-T/sub c/ superconductor sampler circuits using Josephson transmission line buffers

We report on an increase of the measurement bandwidth of a high-T/sub c/ superconductor sampler circuit. The circuit composes a waveform measurement system, in which it is cooled by a compact single-stage cryocooler and operates at a temperature of 35-40 K. In the sampler circuit, there exists a sampling jitter due to thermal fluctuation in the critical current of the pulse generator trigger junction. To reduce the jitter, one can overdrive the trigger junction. However, leakage current into the adjacent sampler element due to parasitic inductance is an obstacle to the use of a larger trigger current. We attempted to suppress the leakage current by inserting a Josephson transmission line (JTL) buffer into the sampler circuit. It was found that a trigger current two-times larger than that of the conventional circuit became possible with the addition of a four-stage JTL and that the frequency at which the measured amplitude decreases by 3 dB increased from 7 GHz to 14 GHz. This result suggests that the jitter was suppressed in the sampler circuit with the JTL buffer.

Analysis of nonuniform ESD current distribution in deep submicron NMOS transistors

This paper presents a detailed study of the nonuniform bipolar conduction phenomenon under electrostatic discharge (ESD) events in single-finger NMOS transistors and analyzes its implications for the design of ESD protection for deep-submicron CMOS technologies. It is shown that the uniformity of the bipolar current distribution under ESD conditions is severely degraded depending on device finger width (W) and significantly influenced by the substrate and gate-bias conditions as well. This nonuniform current distribution is identified as a root cause of the severe reduction in ESD failure threshold current for the devices with advanced silicided processes. Additionally, the concept of an intrinsic second breakdown triggering current (I/sub t2i/) is introduced, which is substrate-bias independent and represents the maximum achievable ESD failure strength for a given technology. With this improved understanding of ESD behavior involved in advanced devices, an efficient design window can be constructed for robust deep submicron ESD protection.

MOSFET triggering silicon controlled rectifiers for electrostatic discharge protection circuits

In this paper we propose a new electrostatic discharge protection circuit called MOSFET-triggering silicon controlled rectifiers (MTSCR) for IC protection. The proposed new SCR circuit consists of a trigger controlling and a holding SCR circuit, and the trigger controlling circuit is made of a pMOSFET with its gate connected to the power supply line. The triggering current is due to the drain current passing through the MOSFET. The circuit can protect IC irrespective of the temporal voltage waveform of the overvoltage stress, and the static trigger voltage decreases with decreasing power supply voltage.

ESD protection under grounded-up bond pads in 0.13 μm eight-level copper metal, fluorinated silicate glass low-k intermetal dielectric CMOS process technology

Electrostatic discharge (ESD) protection device under the grounded-up bond pad is investigated in 0.13 /spl mu/m full eight-level copper metal CMOS process technology with fluorinated silicate glass (FSG) low-k intermetal dielectric (IMD), The bonding force and power produces no cracking and no noticeable change in the second breakdown trigger point (V/sub t2/) I/sub t2/). High current I-V measured from the different level metal layer stack structures shows that 1) I/sub t2/ depends very weakly on metal layers used, as expected due to certain junction power dissipation criterion and 2) V/sub t2/ increases with the number of metal layers, The origin of the latter is increased dynamic impedance for increased metal layer number, as clarified by a simple RC model. The model also yields the intrinsic second breakdown trigger current and voltage for the underlying ESD protection device, Successfully configuring ESD protection circuits under the bond pads, therefore, not only is wholly free from the traditional area consumption, but also can substantially relax design constraints, enabling much more flexible and robust ESD schemes for various applications,.

Quench behavior of the switching elements of a hybrid HTS current limiter

In the hybrid HTS current limiter, current limitation is due to the transition to the normal resistive state of YBCO bars, which are shorting the secondary of a transformer. The HTS bars act as current driven switches allowing two states, a low impedance state in which the bar is in its superconducting state and a higher impedance state arisen after the quench. From the authors' measurements, one can conclude that the triggering current is essentially related to the contact resistance, which induces a hot spot. The resistance developed during the switching time enables the limiter to work. However, the maximum resistance which can be arisen during the quench is limited by the low propagation speed of the transition front, from the contacts to the center of the bars, in the adiabatic approach. In order to stimulate a multi hot spot quench, the authors have adjusted the triggering current by Mg doping the YBCO, thereby homogenizing the quenching current along the bars. They have also developed switching elements based on a quasi isothermal approach of the quench, which diminishes the high thermal gradients developed in the adiabatic quench induced by a hot spot. Measurements of the performances of both switching systems are reported.

Low-voltage triggering for a pseudospark switch with an auxiliary glow discharge

Different electric circuits for triggering the switch with a trigger unit based on an auxiliary glow discharge are discussed. Most attention is concentrated on the recent experimental results on low voltage triggering of the switch and on the mechanisms for the main discharge initiation under the action of the trigger pulse. Due to modifications in the trigger electric circuit, the switch is triggered starting from a voltage of 50 V at a current level in the trigger circuit of 10 mA. With a voltage of 200-250 V and a trigger current of about 0.25 A, the delay time to triggering does not exceed 200 ns.

Comparison of latchup immunity for silicided source/drain at different n + implant energy

The effect of titanium disilicide (TiSi 2) on latchup immunity for different n + source/drain (s/d) junction depth is investigated. Highly latchup immune 0.25 μm CMOS devices have been fabricated with a 50 Ågate oxide, retrograde twin-well and titanium silicided shallow s/d. The trigger current ( I trig) more than doubled from 14 to 32 mA, while the current gain of the npn parasitic BJT ( β) is reduced from 4.9 to 2.5. These improvements are observed when comparing between non-silicided and silicided s/d with shallow junction (at 30 keV). However, when the s/d junction is deep (at 40 keV), the improvement in latchup immunity of silicided s/d over non-silicided s/d decreases. In addition, silicided wafers with shallow junction are more latchup immune than those with deep junction. The above observations are attributed to the reduction of the emitter width and the dopant consumption during TiSi 2 formation, enhanced hole injection due to thinner interfacial oxide, and larger contact area of the silicide and silicon (Si).

Lateral SCR devices with low-voltage high-current triggering characteristics for output ESD protection in submicron CMOS technology

A high-current PMOS-trigger lateral SCR (HIPTSCR) device and a high-current NMOS-trigger lateral SCR (HINTSCR) device with a lower trigger voltage but a higher trigger current are proposed to improve ESD robustness of CMOS output buffer in submicron CMOS technology. The lower trigger voltage is achieved by inserting short-channel thin-oxide PMOS or NMOS devices into the lateral SCR structures. The higher trigger current is achieved by inserting the bypass diodes into the structures of the HIPTSCR and HINTSCR devices. These HIPTSCR and HINTSCR devices have a lower trigger voltage to effectively protect the output transistors in the ESD-stress conditions, but they also have a higher trigger current to avoid the unexpected triggering due to the electrical noise on the output pad when the CMOS ICs are in the normal operating conditions. Experimental results have verified that the trigger current of the proposed HIPTSCR (HINTSCR) is increased up to 225.5 mA (218.5 mA). But, the trigger voltage of the HIPTSCR (HINTSCR) remains at a lower value of 13.4 V (11.6 V). The noise margin against the overshooting (undershooting) voltage pulse on the output pad, without accidentally triggering on the HINTSCR (HIPTSCR), can be greater than VDD+12 V (VSS -12 V). These HIPTSCR and HINTSCR devices have been practically used to protect CMOS output buffers with a 4000-V (700-V) HEM (MM) ESD robustness but only within a small layout area of 37.6/spl times/60 /spl mu/m/sup 2/ in a standard 0.6-/spl mu/m CMOS technology without extra process modification.