Avalanche Breakdown Delay in High-Voltage p-n Junctions Caused by Pre-Pulse Voltage From IEC 61000-4-2 ESD Generators

Abstract

Electrostatic-discharge (ESD) tests with IEC 61000-4-2 generators are often performed at component level but are known to suffer from poor reproducibility. In this paper, it is shown that IEC 61000-4-2 generators can charge the tested device to several tens of volts before the actual ESD pulse is applied. This pre-pulse voltage (PPV) can lead to delayed avalanche breakdown (BD) initiation in silicon junctions. The origin of the BD delay is the emptying of deep trap states within the space-charge region, which lowers the contribution to the generation current due to carrier emission from the deep states. The BD delay is critical for ESD protection devices and can also lead to a dramatic reduction of the snapback trigger current in DMOS transistors. However, transient gate turn-on of the DMOS transistor eliminates the BD delay and can thus increase the ESD robustness. It is shown that the PPV varies strongly between commercial IEC generators, and it is proposed that this could be one of the main reasons for the poor reproducibility of IEC tests. A newly proposed method to deliver an IEC 61000-4-2-shaped pulse through a 50-¿ transmission line is investigated with respect to the correlation with real IEC generators. It is shown that PPV-related issues are not addressed by this method, unless an additional bias voltage is applied during the test. It is also demonstrated that PPV is existent in real-world IEC discharges and must not be neglected for component qualification.