The Impact of CMOS technology scaling on MOSFETs second breakdown: Evaluation of ESD robustness

Abstract

The impact of CMOS technology scaling on the second breakdown of ESD protection devices has been investigated using 2-D simulations and analytical calculations. It is shown that the second breakdown trigger current (It 2 ) can not be reliably used as an ESD robustness criterion in sub-0.18 um ESD protection devices. When a technology feature size is reduced, the doping of drain and drain extension regions is significantly increased. Thus, the ESD device failure due to the self-heating effect occurs without the second snapback region in high current I-V curve and It 2 current can not be properly extracted. Instead of It 2 current criterion, we propose to use the maximum failure temperature criterion.