Transmission Line Pulse Measurements Research Articles

A Standalone Graph-Theory Based Tool for Full-Chip ESD Verification

In this article, a novel flow of the automatic electrostatic discharge (ESD) verification is presented. A basic overview of the most important methodology steps is shown, with more detailed explanation of breaking voltage (BV) model generation. Based on transmission line pulsing measurements, the BV models are used for modeling devices under ESD stress conditions. The principle behind the custom-made tool ESDh is disclosed. Being based on graph-theory algorithm, specifically the Floyd-Warshall algorithm, the tool detects and reconstructs current paths between any node-to-node pair of the integrated circuit (IC). In addition, ESDh can calculate the full current-voltage (IV curve) of any current path. Consequently, this approach is able to find failing paths, failing devices, and failing levels of tested IC. As the method in this work uses the full netlist, without dismissing the core circuitry, ESDh can be used for verifying the self-protection levels of the IC.

Design of a NMOS-triggered SCR for dual-direction low-voltage ESD protection

An improved NMOS triggered dual-direction silicon controlled rectifier (NMOS-DDSCR) device is fabricated in 0.18 μm Silicon-on-Insulator (SOI) Bipolar-CMOS-DMOS (BCD) process. The proposed NMOS-DDSCR structure is designed based on the conventional DDSCR structure, which adds two additional auxiliary trigger paths achieved by NMOS transistors, diodes, and RC coupling circuits. The internal mechanism of NMOS-DDSCR is analyzed using two-dimension (2D) TCAD simulations, and the ESD performance is characterized by means of transmission line pulse (TLP) and very-fast TLP (VFTLP) measurements. Superior to the conventional DDSCR, the proposed NMOS-DDSCR exhibits a lower trigger voltage of 8.2 V, a higher human-body model (HBM) level of 4.0 kV, and a smaller leakage current of about 160 nA for low power application. In addition, the proposed NMOS-DDSCR has lower overshoot voltage, faster turn-on speed, and sufficient latchup immunity, which can be applied to ESD protection of 5.0 V input and output (I/O) pins in smart power integrated circuit (SPIC).

Frequency Based Method Investigation to Extract an ESD Protection Dynamic SPICE Model From TLP Measurement

In order to ensure reliability of systems early in the design phase, it is becoming crucial to have models able to predict the behaviors of systems exposed to electrostatic discharge (ESD). This is an increased necessity since the number of embedded electronic products is growing and since they are involved in applications where people's safety is a requirement. Until now, quasi-static models of protection devices have succeeded in providing fairly good results in failure predictions (mainly hard failures). Today, the increased frequency range of the devices requires dynamic models able to reproduce its transient behavior. In this article, we investigate if conventional modeling methods of linear devices, generally used in frequency domain, could be used to get an equivalent frequency model for ESD protection devices, which exhibit a nonlinear behavior. A methodology to extract an ESD protection SPICE model from transmission line pulse (TLP) measurements to address transient and frequency simulation is proposed and detailed. We will demonstrate that in well-defined conditions, such frequency models can give accurate results to predict overshoots related to protection devices triggering delays. Validation of the models is performed under TLP and human metal model conditions on three off-the-shelf devices.

Analyzing the impact of guard-ring on different dual-direction SCR by device simulation and TLP measurement

In this paper, the impact of the traditional interdigital DDSCR structure (TI-DDSCR) and the embedded DDSCR (EM-DDSCR) structure with and without P+ guard-ring is analyzed under the 0.5-μm complementary and double-diffused MOSFET (CDMOS) technology. In order to verify and predict the characteristics of those electrostatic discharge (ESD) protection devices, a transmission line pulse (TLP) testing system and device simulation platform have been used in this work. The test results show that the introduction of P + guard ring will increase the device forward trigger voltage (Vt1) by about 3 V and forward holding voltage (Vh) by 4-6 V, but has little effect on the forward failure current (It2). The reverse Vh is reduced by 4–6 V, while the reverse It2 depends on the layout geometry. Due to the different layout geometry, on the TI-DDSCR structure with P+ guard ring, their reverse It2 is reduced from 13.07A to 8.05A. On the contrary, on the EM-DDSCR with P+ guard ring, their reverse It2 increased from 6.55A to 10.10A.

All-directional Electrostatic-discharge Protection Circuit with High Area-efficiency

This paper proposes a design for a wholechip all-directional electrostatic-discharge (ESD) protection circuit using a resistor-capacitor (RC) lateral insulated-gate bipolar transistor (LIGBT)-based 12 V power clamp and a silicon-controlled rectifier (SCR)-based 12 V input/output (I/O) clamp. The RC LIGBT-based power clamp detects pulses through an ESD detection circuit and applies a bias to the gate. Therefore, the proposed power clamp does not have snapback curve and has a low impedance during an ESD event. In addition, the structural characteristics of the proposed I/O clamp enable it to provide discharge paths for all four ESD discharge modes (PS, PD, NS, ND), and the clamp is more area efficient than conventional ESD protection circuits composed of gate-grounded n-type metal-oxide-silicon transistors or SCRs. Moreover, because floating regions are inserted in the I/O clamp and the clamp has a high holding voltage, the clamp design is resistant to latch-up, which is a critical drawback of snapback devices. Therefore, the proposed ESD protection circuit can effectively provide highly reliable protection to internal integrated circuits. The proposed circuit was fabricated using a 0.18 ㎛ bipolar-CMOS-DMOS process, and the electrical properties and ESD robustness of the circuit were verified through a transmission line pulse measurement method and human body model surge application tests.

Silicon-controlled Rectifier-based Electrostatic Discharge Protection Circuit with Additional NPN Parasitic Bipolar Junction Transistor for 5-V Application

This paper proposes a novel protection circuit based on a silicon-controlled rectifier (SCR) to prevent electrostatic discharge (ESD) at low voltages. The proposed device consists of an additional NPN parasitic bipolar transistor operated via application of an N+ diffusion region and a well breakdown voltage, to reduce the high trigger voltage caused by the well breakdown voltage of the existing SCR structure. Furthermore, the proposed device exhibits an improved trigger voltage, holding voltage, and dynamic resistance component when compared with existing parasitic PNP bipolar transistors. The proposed ESD protection circuit was manufactured using a 0.18 μm bipolar-CMOS-DMOS; it exhibited a significant improvement in electrical characteristics such as trigger voltage (8.1 V) and holding voltage (3.55 V), according to the results of transmission line pulse measurement. Hence, it is deemed to be suitable for 5-V-class applications.

Design of a cascade-MOS-triggered SCR with high holding-voltage for high-voltage ESD protection

A parallel-MOS-triggered silicon-controlled rectifier (PMTSCR) is firstly proposed and verified in a 0.25-μm Bipolar-CMOS-DMOS process, aiming to prevent the latch-up effect of SCR in the electrostatic discharge (ESD) protection. Comparing to the conventional SCR, the trigger voltage (Vt1) of the PMTSCR decreases because of the effect of PMOS embedded in the N-well, and the holding voltage (Vh) increases because of the attribution of the NMOS embedded in the P-well. By shortening the SCR current conduction path and designing a special metal connection, the modified-PMTSCR (M-PMTSCR) is obtained. The failure current of the M-PMTSCR remarkably increases from 1.8 to 4.8 A. However, M-PMTSCR exhibits a lower Vh and a higher Vt1. By further optimizing the location and connection of the embedded PMOS and NMOS, the obtained cascade-MOS-triggered SCR (CMTSCR) possesses a high Vh of 8.4 V and a strong ESD robustness of 6000 V in a small chip area. Meanwhile, the operation mechanism simulated by Sentaurus was consistent with the theoretical circuit analysis and transmission line pulse measurements. Thus the proposed CMTSCR with the good latch up immunity and temperature stability is a promising device to meet the requirements of high voltage ESD protection.

A compact LDMOS DDSCR for HV ESD protections with high robustness and reliability

The LDMOS-based silicon controlled rectifier (SCR) is commonly used in high voltage (HV) electrostatic discharge (ESD) protection due to its great current handling capability per area and HV protection ability. In this paper, an improved LDMOS-based dual direction SCR (LDMOS-DDSCR) device is designed by replacing floating N+ region with electrically-connected P+, N+ and P+ regions to enhance its ESD robustness, which is verified in a 0.5-μm (1p2m) 18 V HV CDMOS process. The internal mechanism of the proposed device is analyzed using two-dimension (2D) TCAD simulations, and the ESD performance is characterized by means of transmission line pulse (TLP) and very-fast TLP (VFTLP) measurements. Compared with the conventional LDMOS-DDSCR, the failure current of the compact LDMOS-DDSCR raises from 2.00 A to 4.02 A (increased by 101%), and the trigger voltage reduces from 44.28 V to 39.76 V, without sacrificing layout area. Furthermore, the TLP I-V curves of the proposed LDMOS-DDSCR are measured at different temperatures ranging from 25 °C to 125 °C, which proves its reliability and show potential use in the applications of high voltage integrated circuits.

ESD Protection Diodes in Bulk Si Gate-All-Around Vertically Stacked Horizontal Nanowire Technology

For sub-5 nm bulk Si CMOS, a gate-all-around (GAA) nanowire (NW) device is a promising candidate. The new device architecture will have an impact on the transient performance of an electrostatic discharge protection diode. The 100 ns transmission line pulse (TLP) and 2 ns very fast TLP measurement results and TCAD simulations prove that the performance in bulk GAA NW-based diodes is maintained in comparison to bulk FinFET diodes.

Methodology for Analyzing ESD-Induced Soft Failure Using Full-Wave Simulation and Measurement

An analysis methodology is presented to investigate soft failures in electronic devices. This methodology combines transmission line pulse (TLP) full-wave simulations with system-level and TLP measurements. Information on susceptible parts in the device under test (DUT) and/or soft failure sensitivity of the integrated circuits (ICs) are obtained from the measurements. Then, the TLP current spreading within the printed circuit board (PCB) of the DUT is simulated. The susceptible signals can be determined by comparing the simulated voltages and/or currents at the signal terminations with the measured threshold values. If the simulated voltages and/or currents are higher than the threshold values, the signal is considered susceptible and a soft failure may occur in the DUT. Using the obtained information from simulations and measurements, the root causes of soft failures can be identified. Further, by utilizing full-wave simulations, the design of the product can be modified to reduce the electrostatic discharge (ESD) noise on the susceptible signals, and consequently prevent soft failures. The proposed analysis methodology is applied to a tablet which suffers from soft failure. The root cause of the soft failure is identified, and countermeasures are designed against the ESD-induced soft failure.

SCR-Based ESD Protection Using a Penta-Well for 5 V Applications

This paper proposes a new structure of silicon controlled rectifier (SCR)-based ESD protection circuit using a penta-well for ESD protection in 5 V applications. The proposed circuit exhibits higher holding voltage and current-driving capability than low Ron SCR (LRSCR) ESD protection circuits. The existing LRSCR ESD protection circuit and the proposed ESD protection circuit were fabricated using the 0.18 $\mu$ m BCD process. The electrical and latch-up characteristics were compared and analyzed using transmission line pulse measurement and a transient-induced latch-up test.

Transmission Line Pulse Test Method for Estimating SEB Performance of $n$ -Channel Lateral DMOS Power Transistors

A novel wafer-level method is described for predicting lateral-diffused MOS transistor single-event burnout (SEB) levels to assist device engineers in the development phase of radiation-hardened power transistors. The method uses a transmission-line pulse (TLP) tester together with scribe-line transistor test structures. Technology computer-aided design (TCAD) is used to estimate static $I_{d} - V_{\mathrm {dss}}$ behavior and device transient response to heavy ion strikes. Various comparisons are made between TCAD, TLP measurements, and heavy ion testing. TCAD simulations provide physical justification for using TLP measurements to estimate SEB.

Investigation on Electrostatic Discharge Robustness of Gate-All-Around Silicon Nanowire Transistors Combined With Thermal Analysis

In this letter, we investigate the robustness of silicon-on-insulator-based gate-all-around silicon nanowire transistors (GAA SNWTs) subject to electrostatic discharge (ESD) stress by thermal analysis and transmission line pulse measurements. The thermal conductance modeling shows that heat dissipation, from channel to substrate through gate oxide, gate electrode, and buried oxide, dominates the thermal failure mechanism and thus the intrinsic ESD performance in GAA SNWTs. Accordingly, a new GAA SNWT is proposed and fabricated. A record failure current density of 18.8 mA/μm is achieved at a nanowire diameter of 5 nm and a gate length of 500 nm. The impact of device parameters on ESD performance is also studied to give the guidance for the future ESD design with silicon nanowire transistors.

Impacts of Leakage-Biasing Failure-Mode Identification in the Transmission-Line Pulse Testing for Low-/High-Voltage MOSFET Components

The effects of leakage-biased voltage ( V LB) levels are investigated in this paper, which are set for failure-mode identification on the final fault diagnostic measurement in transmission line pulse (TLP) testing. To identify the effect on electrostatic discharge (ESD) robustness, three types of MOSFET components were employed; namely, low-voltage n -channel MOSFET (LVnMOS) (5 V/0.6 μm), high-voltage n-channel MOSFET (HVnMOS), and high-voltage p-channel MOSFET (HVpMOS) (12 V/1.8 μm) devices under test (DUTs), respectively. After a series of systematic TLP measurements, this study determined that the set VLB level substantially influenced the failure mode identification and I t2 value decision on the LVnMOS and HVnMOS DUTs, but its effect on the HVpMOS DUT was extremely weak. According to the secondary breakdown current ( I t2) values, the error caused by a maximum V LB level was up to 55.6% in the LVnMOS DUT, 81% in the HVnMOS DUT, and only 3.38% in the HVpMOS DUT. Consequently, this engendered a considerable deviation in most data derived from testing DUTs through TLP compared with those derived from a human-body model (HBM). Hence, to ensure a high correlation between values measured through TLP testing NNand an HBM for the same DUTs, the V LB level should be considered during TLP testing. The lack of correlation is demonstrated to be due to a moderate soft and hard failure during TLP measurement especially for the LVnMOS and HVnMOS samples. Therefore, to obtain accurate I t2 values for DUTs, the V LB level for the failure-mode identification in TLP testing should be within a low-biasing range (such as kept V LB ≤ 5 V).

Low Ron and high robustness ESD protection design for low‐voltage power clamp application

An electrostatic discharge (ESD) protection circuit with novel structure based on a silicon-controlled rectifier (SCR) is proposed for 5 V ESD protection of integrated circuits. The proposed ESD protection circuit has large current driving capacity due to its low on-resistance and high ESD robustness in comparison with the conventional SCR-based ESD protection circuit. The conventional SCR-based ESD protection circuit and the proposed ESD protection circuit were fabricated using a 0.18 µm bipolar CMOS-double diffused metal-oxide semiconductor transistor (DMOS) process, and their electrical characteristics and ESD robustness were comparatively analysed using transmission line pulse measurements.

An ultralow‐capacitance bidirectional punch‐through transient voltage suppressor

A bidirectional punch‐through transient voltage suppressor based on a five‐layer N++P+PP+N++ structure is developed. By realizing the device using a 12‐finger layout, transmission line pulse measurements indicate that the device has met the IEC61000‐4‐2 standard with electrostatic discharge robustness of ±8 kV and has an ultralow capacitance value of less than 0.17 pF. Under 3.3 V forward or reverse bias, the device exhibits a leakage current of less than 2 nA. These excellent figures suggest that the developed structure is well suited for actual system‐level protection applications. © 2016 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.

Systematic Characterization of Graphene ESD Interconnects for On-Chip ESD Protection

We report systematic transient characterization of a graphene ribbon (GR) used as an interconnect for electrostatic discharge (ESD) protection of future integrated circuits. A large set of GR wires (around 6000) with varying and practical dimensions were fabricated using the chemical vapor deposition method and characterized by transmission line pulsing (TLP) and very fast TLP (VFTLP) measurements. Comprehensive TLP and VFTLP testing with varying pulse rise time ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$t_{r})$ </tex-math></inline-formula> and duration ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$t_{d})$ </tex-math></inline-formula> was performed across a wide temperature range ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$T = -30/+110~^{\circ }\text{C}$ </tex-math></inline-formula> ). Measurement-based statistics reveal the relationship between ESD capability of GR wires and the wire length ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$L$ </tex-math></inline-formula> ), width ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$W$ </tex-math></inline-formula> ), and number of graphene layers, as well as ESD pulse shapes and operation temperature.

Diode triggered ESD power clamp circuit with accurate discharge duration

A new diode triggered power clamp circuit is proposed. It adopts diode strings to detect electrostatic discharge event and avoid mis-triggering. By considering the amount of ESD charges in different power-on ESD events, a compensation circuit with a new turn-off mechanism is presented to accurately control the discharge duration, and this mechanism is validated by simulation. The circuit is fabricated in a 0.18 μm 1.8 V CMOS process, and the ESD performance is verified by the transmission line pulse measurement.

Design of SCR-Based ESD Protection Circuit for 3.3 V I/O and 20 V Power Clamp

In this paper, MOS-triggered silicon-controlled rectifier (SCR)-based electrostatic discharge (ESD) protection circuits for mobile application in 3.3 V I/O and SCR-based ESD protection circuits with floating N+/P+ diffusion regions for inverter and light-emitting diode driver applications in 20 V power clamps were designed. The breakdown voltage is induced by a grounded-gate NMOS (ggNMOS) in the MOS-triggered SCR-based ESD protection circuit for 3.3 V I/O. This lowers the breakdown voltage of the SCR by providing a trigger current to the P-well of the SCR. However, the operation resistance is increased compared to SCR, because additional diffusion regions increase the overall resistance of the protection circuit. To overcome this problem, the number of ggNMOS fingers was increased. The ESD protection circuit for the power clamp application at 20 V had a breakdown voltage of 23 V; the product of a high holding voltage by the N+/P+ floating diffusion region. The trigger voltage was improved by the partial insertion of a P-body to narrow the gap between the trigger and holding voltages. The ESD protection circuits for low- and high-voltage applications were designed using Bipolar-CMOS-DMOS technology, with width. Electrical characteristics and robustness are analyzed by a transmission line pulse measurement and an ESD pulse generator (ESS-6008).

In-Depth Electromagnetic Analysis of ESD Protection for Advanced CMOS Technology During Fast Transient and High-Current Surge

The purpose of this paper is to present the main results of an electrostatic discharge (ESD) protection for advanced CMOS technology with electromagnetic (EM) field effect and Lorentz Force (LF) contributions during fast transient and high-current surge. To address this goal, the first step is building a tool to simulate fast transient conditions with all participating physical mechanisms included. The relevant equations describing these mechanisms are: 1) the charge transport equations and 2) the Maxwell equations to describe the EM fields. The LF is also included using an extended formulation of the current-continuity equations. An integrated approach is followed to simulate the full structure (metal connections $+$ silicon device) during the ESD surge and to compare the results between ElectroMagnetic Lorentz Force simulations and transmission line pulse measurements. Obviously, in general, this paper and tool can be used to address electromagnetic compatibility topics and more.