A Standalone Graph-Theory Based Tool for Full-Chip ESD Verification

Abstract

In this article, a novel flow of the automatic electrostatic discharge (ESD) verification is presented. A basic overview of the most important methodology steps is shown, with more detailed explanation of breaking voltage (BV) model generation. Based on transmission line pulsing measurements, the BV models are used for modeling devices under ESD stress conditions. The principle behind the custom-made tool ESDh is disclosed. Being based on graph-theory algorithm, specifically the Floyd-Warshall algorithm, the tool detects and reconstructs current paths between any node-to-node pair of the integrated circuit (IC). In addition, ESDh can calculate the full current-voltage (IV curve) of any current path. Consequently, this approach is able to find failing paths, failing devices, and failing levels of tested IC. As the method in this work uses the full netlist, without dismissing the core circuitry, ESDh can be used for verifying the self-protection levels of the IC.