Abstract
In this paper, the impact of the traditional interdigital DDSCR structure (TI-DDSCR) and the embedded DDSCR (EM-DDSCR) structure with and without P+ guard-ring is analyzed under the 0.5-μm complementary and double-diffused MOSFET (CDMOS) technology. In order to verify and predict the characteristics of those electrostatic discharge (ESD) protection devices, a transmission line pulse (TLP) testing system and device simulation platform have been used in this work. The test results show that the introduction of P + guard ring will increase the device forward trigger voltage (Vt1) by about 3 V and forward holding voltage (Vh) by 4-6 V, but has little effect on the forward failure current (It2). The reverse Vh is reduced by 4–6 V, while the reverse It2 depends on the layout geometry. Due to the different layout geometry, on the TI-DDSCR structure with P+ guard ring, their reverse It2 is reduced from 13.07A to 8.05A. On the contrary, on the EM-DDSCR with P+ guard ring, their reverse It2 increased from 6.55A to 10.10A.
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