A Robust Scalable ESD Protection Device integrating Drain side Floating P+ Diffusion with tunable ESD Design Window and effective Latch-up immunity for High-Voltage Power Clamp applications

Abstract

A footprint-efficient Electrostatic Discharge (ESD) protection device integrating Drain side Floating P+ Diffusion was evaluated for effective High Voltage (HV) Supply Pin ESD protection in a 130nm GlobalFoundries <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">®</sup> low-cost BCDLite process. Conventional Medium Voltage (MV) Gate-Grounded N-type Metal-Oxide-Semiconductor (GGNMOS) ESD protection devices are typically limited in terms of voltage applications (up to 5V). Tunability of the trigger and holding voltages is the key to developing power clamps with adaptable ESD Design Window and high Latch-up immunity, covering a wide voltage spectrum. Influence of Drain N+ Diffusion pullback from Gate edge, effect of background P-body doping modulation and impact of critical design parameters pertaining to the dimension and position of the Floating P+ Diffusion relative to the Gate and Drain terminals on the ESD performance of the device are evaluated. A scalable device architecture suitable for 8V (stand-alone) to 40V (stacked) power clamp applications without using an additional mask with best-in-class DC & 100ns Transmission Line Pulse (TLP) performance from Technology Computer-Aided Design (TCAD) simulations and silicon measurement results is demonstrated.