Design of a cascade-MOS-triggered SCR with high holding-voltage for high-voltage ESD protection

Abstract

A parallel-MOS-triggered silicon-controlled rectifier (PMTSCR) is firstly proposed and verified in a 0.25-μm Bipolar-CMOS-DMOS process, aiming to prevent the latch-up effect of SCR in the electrostatic discharge (ESD) protection. Comparing to the conventional SCR, the trigger voltage (Vt1) of the PMTSCR decreases because of the effect of PMOS embedded in the N-well, and the holding voltage (Vh) increases because of the attribution of the NMOS embedded in the P-well. By shortening the SCR current conduction path and designing a special metal connection, the modified-PMTSCR (M-PMTSCR) is obtained. The failure current of the M-PMTSCR remarkably increases from 1.8 to 4.8 A. However, M-PMTSCR exhibits a lower Vh and a higher Vt1. By further optimizing the location and connection of the embedded PMOS and NMOS, the obtained cascade-MOS-triggered SCR (CMTSCR) possesses a high Vh of 8.4 V and a strong ESD robustness of 6000 V in a small chip area. Meanwhile, the operation mechanism simulated by Sentaurus was consistent with the theoretical circuit analysis and transmission line pulse measurements. Thus the proposed CMTSCR with the good latch up immunity and temperature stability is a promising device to meet the requirements of high voltage ESD protection.