Investigation on Electrostatic Discharge Robustness of Gate-All-Around Silicon Nanowire Transistors Combined With Thermal Analysis

Abstract

In this letter, we investigate the robustness of silicon-on-insulator-based gate-all-around silicon nanowire transistors (GAA SNWTs) subject to electrostatic discharge (ESD) stress by thermal analysis and transmission line pulse measurements. The thermal conductance modeling shows that heat dissipation, from channel to substrate through gate oxide, gate electrode, and buried oxide, dominates the thermal failure mechanism and thus the intrinsic ESD performance in GAA SNWTs. Accordingly, a new GAA SNWT is proposed and fabricated. A record failure current density of 18.8 mA/μm is achieved at a nanowire diameter of 5 nm and a gate length of 500 nm. The impact of device parameters on ESD performance is also studied to give the guidance for the future ESD design with silicon nanowire transistors.