Transistor Logic Research Articles

Ultra‐low‐voltage GDI‐based hybrid full adder design for area and energy‐efficient computing systems

In recent years, ultra-low-voltage (ULV) operation is gaining more importance for achieving minimum energy consumption. Full adder is the basic computational arithmetic block in many of the computing and signal/image processing applications. Here, a new hybrid 1-bit full adder circuit which employs both Gate Diffusion Input (GDI) logic and multi-threshold voltage (MVT) transistor logic is reported. The main objective of the proposed MVT-GDI-based hybrid full adder design is to provide minimum energy consumption with less area. The proposed hybrid design is simulated using standard 45 nm CMOS process technology at an ULV of 0.2 V. The post-layout simulation results have shown that the proposed design achieved significant improvements in comparison with the other reported designs by achieving >57%, 92% savings in the Energy and EDP, respectively, with only 14 transistors. Monte–Carlo simulations have also been performed and is found that the proposed design methodology yields full functionality and robustness against local and global process variations. Normalised energy metrics to 32 and 22 nm technologies shows that the proposed design achieves >57% energy savings in prior to the recent works.

Small footprint transistor architecture for photoswitching logic and in situ memory.

The need for continuous size downscaling of silicon transistors is driving the industrial development of strategies to enable further footprint reduction1,2. The atomic thickness of two-dimensional materials allows the potential realization of high-area-efficiency transistor architectures. However, until now, the design of devices composed of two-dimensional materials has mimicked the basic architecture of silicon circuits3-6. Here, we report a transistor based on a two-dimensional material that can realize photoswitching logic (OR, AND) computing in a single cell. Unlike the conventional transistor working mechanism, the two-dimensional material logic transistor has two surface channels. Furthermore, the material thickness can change the logic behaviour-the architecture can be flexibly expanded to achieve in situ memory such as logic computing and data storage convergence in the same device. These devices are potentially promising candidates for the construction of new chips that can perform computing and storage with high area-efficiency and unique functions.

LECTOR incorporated differential cascode voltage swing logic (L-DCVSL)

This contribution aims at incorporating leakage control transistors (LCTs) in differential cascode voltage swing logic (DCVSL) to reduce leakage and is named as L-DCVSL. The concept multi threshold is also introduced in LCTs and resulting static, dynamic and enhanced DCVSL variants are referred as MTL-DCVSL, MTL-dyDCVSL and MTL-EDCVSL. The performance at 90 nm, 65 nm, and 45 nm technology nodes is investigated using SymicaDE tool. Two input exclusive OR/NOR (XOR2/XNOR2) gate is used to illustrate the proposed technique due to its extensive use in arithmetic cores. The leakage current is examined in all the examples and it is found that leakage current decreases with scaling down of geometry. Maximum saving in leakage current is observed to be 81.27% while minimum is 44.18% for MTL-DCVSL. Similar observations for MTL-dyDCVSL and MTL-EDCVSL are (12.24%, 9.52%)/(33%, 66.04%) and (16.06%, 61.67%)/(37.11%, 78.45%) respectively for precharge/evaluate state. Effect of temperature is also investigated and it is found that leakage current in both static and dynamic configurations of DCVSL follows a directly proportional behaviour with respect to temperature.

Design and comparative analysis of D-Flip-flop using conditional pass transistor logic for high-performance with low-power systems

Flip-flop is one of the essential elements of data path structure design in the digital era. In this paper, the peculiar Flip-flop topologies, called as Conditional Pass Logic Static D-Flip-Flop (CPLSDFF) and Conditional Pass Logic Dynamic D-Flip-Flop (CPLDDFF) are proposed. The main objective of the proposed system is to optimize the primary performance criterions such as area and power. The first parameter is attained by reducing the device count, and the later is achieved by removing the redundant transistor switching, charge sharing and frequent power consumption from the source. The CPLSDFF and CPLDDFF are designed using SPICE with 130 nm IBM transistor technology and it shows that the silicon area is reduced up to 27% and 22% respectively. The conditional pass-transistor logic method is introduced in the proposed system leads to minimizing the unnecessary switching activity, charge sharing in intermediate nodes and power utilization is also minimized up to 12% in the static model, 70% in the dynamic model. The various performance parameters like transistor count, the clock driving power, data driving power, switching activity and propagation delay (D-Q) of the Flip-flop are investigated in detail and are correlated with the existing designs. The optimized CPLFF structures are also employed in 8-bit serial in serial out (SISO) shift registers and can save power up to 35% and 42% respectively. The outcomes show that the proposed system is most adaptable for low power applications with superior performance in register designs.

Towards Silicon Carbide VLSI Circuits for Extreme Environment Applications

A Process Design Kit (PDK) has been developed to realize complex integrated circuits in Silicon Carbide (SiC) bipolar low-power technology. The PDK development process included basic device modeling, and design of gate library and parameterized cells. A transistor–transistor logic (TTL)-based PDK gate library design will also be discussed with delay, power, noise margin, and fan-out as main design criterion to tolerate the threshold voltage shift, beta ( β ) and collector current ( I C ) variation of SiC devices as temperature increases. The PDK-based complex digital ICs design flow based on layout, physical verification, and in-house fabrication process will also be demonstrated. Both combinational and sequential circuits have been designed, such as a 720-device ALU and a 520-device 4 bit counter. All the integrated circuits and devices are fully characterized up to 500 °C. The inverter and a D-type flip-flop (DFF) are characterized as benchmark standard cells. The proposed work is a key step towards SiC-based very large-scale integrated (VLSI) circuits implementation for high-temperature applications.

ZnO composite nanolayer with mobility edge quantization for multi-value logic transistors

A quantum confined transport based on a zinc oxide composite nanolayer that has conducting states with mobility edge quantization is proposed and was applied to develop multi-value logic transistors with stable intermediate states. A composite nanolayer with zinc oxide quantum dots embedded in amorphous zinc oxide domains generated quantized conducting states at the mobility edge, which we refer to as “mobility edge quantization”. The unique quantized conducting state effectively restricted the occupied number of carriers due to its low density of states, which enable current saturation. Multi-value logic transistors were realized by applying a hybrid superlattice consisting of zinc oxide composite nanolayers and organic barriers as channels in the transistor. The superlattice channels produced multiple states due to current saturation of the quantized conducting state in the composite nanolayers. Our multi-value transistors exhibited excellent performance characteristics, stable and reliable operation with no current fluctuation, and adjustable multi-level states.

Triple transistor based triple modular redundancy with embedded voter circuit

This paper presents a new static redundancy technique that combines the redundancy at transistor level with redundancy at functional level and offers a very good reliability at minimal increase in the hardware, delay and power overheads. The proposed method does not require any external voter hardware as in triple modular redundancy (TMR) method; instead the last level gates of the triplicated modules of the circuit are combined and designed using fault tolerant triple transistor logic which act as an embedded voter circuit. This method offers higher reliability at lesser area and shorter critical path compared to the most popular TMR method as well as other recently proposed static fault tolerant methods. This makes our design suitable for designing fault tolerant systems for real-time resource constrained applications. We have provided theoretical analysis as well as simulation results proving the superiority of our method.

Simple low power nanosecond pulses from a continuous wave diode laser.

A low power continuous wave diode laser is rapidly modulated using the inherent propagation delay and finite slew rate of an inverter to create overlapping time transistor-transistor logic pulses to activate an AND gate to create sub-nanosecond laser pulses at user controller repetition rate up to 100 KHz.

Synaptic Resistors for Concurrent Inference and Learning with High Energy Efficiency.

The fastest supercomputer, Summit, has a speed comparable to the human brain, but is much less energy-efficient (≈1010 FLOPS W-1 , floating point operations per second per watt) than the brain (≈1015 FLOPS W-1 ). The brain processes and learns from "big data" concurrently via trillions of synapses in parallel analog mode. By contrast, computers execute algorithms on physically separated logic and memory transistors in serial digital mode, which fundamentally restrains computers from handling "big data" efficiently. The existing electronic devices can perform inference with high speeds and energy efficiencies, but they still lack the synaptic functions to facilitate concurrent convolutional inference and correlative learning efficiently like the brain. In this work, synaptic resistors are reported to emulate the analog convolutional signal processing, correlative learning, and nonvolatile memory functions of synapses. By circumventing the fundamental limitations of computers, a synaptic resistor circuit performs speech inference and learning concurrently in parallel analog mode with an energy efficiency of ≈1.6 × 1017 FLOPS W-1 , which is about seven orders of magnitudes higher than that of the Summit supercomputer. Scaled-up synstor circuits could circumvent the fundamental limitations in computers, and facilitate real-time inference and learning from "big data" with high efficiency and speed in intelligent systems.

Random signal generation and synchronization in lab-scale measurement device independent–quantum key distribution systems

In this paper, a random transistor-transistor logic signal generator and a synchronization circuit are designed and implemented in lab-scale measurement device independent–quantum key distribution systems. The random operation of the weak coherent sources and the system’s synchronization signals were tested by a time to digital convertor.

Phase Voltage Measurement for Permanent Magnet Machine Sensorless Drive Using Controller Capture Modulator

This paper improves the position sensorless drive by sensing actual machine phase voltages. A high-bandwidth phase voltage measurement is developed for pulsewidth modulation (PWM) voltage inverters. On the basis, the actual phase voltage is obtained based on the digital integration of PWM voltage using the capture modulator in existing drive microcontrollers (MCU's). Comparing to existing phase voltage measurement, no separated A/D converter and communication hardware are required because PWM pulses are directly measured using MCUs. However, for standard machines without neutral points, only line-to-line ac PWM voltages can be measured for the phase voltage reconstruction. Since the capture based on transistor-transistor logic (TTL) logics receives only digital signals, a preprocess circuit to convert ac PWM line voltages to equivalent digital signals is proposed. This paper clearly explains the voltage sensing hardware using MCU capture modulator. According to experimental results, a 150-MHz sampling rate for phase voltage measurement is achieved based on the proposed capture-based voltage measurement. Although the physical limitation of back electromotive force estimation still appears, the proposed phase voltage measurement substantially enhances the sensorless drive performance at low speed.

Incomplete Dipoles Flipping Produced Near Hysteresis-Free Negative Capacitance Transistors

In this letter, we experimentally investigate the impact of polarization (P) switching behaviors on hysteretic and near hysteresis-free (NHF) negative capacitance field-effect transistors (NCFETs). Compared with the typical abrupt P switching in hysteretic devices, NHF NCFETs show gradual and continuous response of P under applied voltage, indicating that the mechanism underlying NHF characteristics is incomplete dipoles flipping, rather than complete dipoles switching. It has also been confirmed by a small amount of P charge (0.1~0.2 μC/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ), which is still capable of achieving electrical performance improvement. This favors the device operation voltage scaling and reliability improvement for logic transistor applications.

Solution-processed organic-inorganic hybrid gate insulator for complementary thin film transistor logic circuits

In this work, we demonstrated a poly(4-vinylphenol-co-methyl methacrylate) (PVP-co-PMMA)/Al2O3 double-stacked insulator deposited by solution process. The double-stacked insulator exhibited higher degree of performance uniformity than individual single-stacked insulators. We fabricated an inverter circuit in order to demonstrate the applicability of the proposed insulator in complementary logic circuits, which are composed of metal oxide thin film transistors as the n-channel device and organic thin film transistors as the p-channel device. We utilized amorphous indium gallium zinc oxide thin film transistor and pentacene thin film transistor for the n-channel and p-channel devices, respectively. It was observed that the PVP-co-PMMA/Al2O3 double-stacked insulator had the effect of overcoming the problems related to individual single-stacked layers, such as high leakage current of Al2O3 and low dielectric constant of PVP-co-PMMA. The inverter operated at a threshold voltage of 1.5 V and exhibited high voltage gain of 17.3 V/V at the supply voltage of 3 V.

A Review of Constant Delay Logic at 90nm CMOS Technology

This paper presents the review work on Constant Delay (CD) Logic. Dynamic (Complementary Metal Oxide Semiconductor) CMOS circuit style is introduced which allows to reduce number of transistors for implementing any logic. (Feed Through Logic) FTL overcomes the use of more transistors in dynamic domino logic, this use implement using the same number of transistors required in dynamic logic. The CD Logic generates the high speed of operation of possible circuits. The timing window technique is analyzed which is mainly for the reduction of power dissipation i.e., reduction of the evaluation time. CD Logic display a rare aspect where the output is pre-evaluated before the input from the previous stage is ready. This property offers good performance analysis over the dynamic and static logic style.CD Logic reducing the charging current with the support of Leakage current. Using 90nm CMOS technology, different circuits based on CD Logic is analyzed for power, delay, (Power Delay Product) PDP and noise calculation.

Improved low power implicit pulse triggered flip-flop with reduced power dissipation

In this paper, an improved implicit pulse triggered flip-flop is proposed based on conditional pulse enhancement scheme. The pass transistor logic AND gate creates a faster discharge path. Then a conditional pulse enhancement scheme is used in order to conditionally enhance the pulse only when required. This avoids unnecessary switching action in the flip-flop. Then in order to reduce the power dissipation further, the pseudo NMOS logic is replaced with a NAND gate structure. This reduces the static power consumption and as well as the switching power consumption. Thus results in an overall power saving. The results are obtained in 180 nm CMOS technology using mentor graphics. The results are compared with four conventional flip-flops and its power saving is improved.

DESIGN OF A HIGH SPEED HYBRID TRANSISTOR LOGIC (HTL) MULTIPLIER USING HTL ADDER

Ponte Academic JournalNov 2019, Volume 75, Issue 11 DESIGN OF A HIGH SPEED HYBRID TRANSISTOR LOGIC (HTL) MULTIPLIER USING HTL ADDERAuthor(s): P. Manju ,T. MadhaviJ. Ponte - Nov 2019 - Volume 75 - Issue 11 doi: 10.21506/j.ponte.2019.11.7 Abstract:In cryptographic applications modular multiplications are most widely used. This modular multiplication depends on the addition and shifting operations. While performing iteration operation in modular multiplication, right shift operation with complete word architecture is performed. In the same way arithmetic unit is used in the multiplier to perform the arithmetic operations. While designing arithmetic unit, optimized multipliers are used most widely. Here a high speed hybrid multiplier using hybrid transistor logic adder is presented in this paper. This advanced Montgomery modular multiplication is based on the modular exponentiations to obtain high speed. The Montgomery multiplication uses adequate hardware implementation. The hybrid transistor logic multiplier system not only depends on the modular exponentiations but also depends on the modular multiplication to reduce the delay. Hence compared to Hybrid transistor logic adder system, the hybrid transistor logic multiplier system gives effective results in terms of speed, area and delay. Download full text:Check if you have access through your login credentials or your institution Username Password

Junctionless Field Effect Diode (JL-FED): A First-Principles Study

This paper proposes a novel field effect diode (FED) for the first time namely junctionless FED (JL-FED). Our simulation results show that JL-FED gives the combined advantages of conventional FED and JL field effect transistor (JL-FET). In fact, not only fabrication process of the JL-FED is easier than FED, but also unlike a FED, JL-FED device turns on without applied biases to the control gates. Furthermore, to reduce the leakage current of the JL-FED structure, we propose modified JL-FED (MJL-FED) structure, in which the control gates work functions are different from that of JL-FED. The digital performance parameters such as ION/IOFF ratio and subthreshold slope (SS) for MJL-FED are investigated using 2-D simulations. MJL-FED offers superior ION/IOFF ratio and SS than its JL-FED counterpart having same dimensions. Our simulation results show that MJL-FED provides channel length scaling possible down to 10 nm, and it is a reasonable candidate for logic transistor applications.

A simplified LED-driven switch for fast-scan controlled-adsorption voltammetry instrumentation.

Fast-scan cyclic voltammetry (FSCV) is an analytical tool used to probe neurochemical processes in real-time. A major drawback for specialized applications of FSCV is that instrumentation must be constructed or modified in-house by those with expertise in electronics. One such specialized application is the newly developed fast-scan controlled-adsorption voltammetry (FSCAV) that measures basal (tonic) in vivo dopamine and serotonin concentrations. FSCAV requires additional software and equipment (an operational amplifier coupled to a transistor-transistor logic) allowing the system to switch between applying a FSCV waveform and a constant potential to the working electrode. Herein we describe a novel, simplified switching component to facilitate the integration of FSCAV into existing FSCV instruments, thereby making this method more accessible to the community. Specifically, we employ two light emitting diodes (LEDs) to generate the voltage needed to drive a NPN bipolar junction transistor, substantially streamlining the circuitry and fabrication of the switching component. We performed in vitro and in vivo analyses to compare the new LED circuit vs. the original switch. Our data shows that the novel simplified switching component performs equally well when compared to traditional instrumentation. Thus, we present a new, simplified scheme to perform FSCAV that is cheap, simple, and easy to construct by individuals without a background in engineering and electronics.

Magnetic resonance imaging of strain in elastic gels

Magnetic resonance imaging (MRI) can also be used for studying different material conditions, including strain, which is the subject of this study. A pair of pulsed magnetic field gradients combined with the spin-echo imaging sequence [pulsed-gradient spin-echo (PGSE)] enables the detection of small sample displacements that are induced in the time between the gradient pulses. The displacements are registered in the image phase shift, which is then processed by the phase unwarping algorithm and phase background correction. The processed phase shift can then be used to calculate sample displacements by multiplying it with the corresponding calibration constant. Finally, the strain tensor can be calculated from the map of sample displacements. In the study, the PGSE imaging method was tested on a gelatin sample. While being MRI scanned, the sample was deformed synchronously with the imaging sequence using a special MRI-compatible apparatus for inducing sample deformations. The apparatus was based on the use of compressed air that was directed via a nozzle on the surface of the sample in pulses controlled by transistor-transistor logic pulses of the spectrometer. With the 20 ms pulses of compressed air at a pressure of 0.5 bar, sample displacements of up to 300 μm were detected at the impact point of compressed air, while the detection threshold was at 0.7 μm. Results of the PGSE method were also compared with the tagging method. The study was performed in 2D; however, the method can be implemented also in 3D, thus enabling the measurement of the full strain tensor.

An uncertainty analysis of the time-resolved fuel injection pressure wave based on BOSCH method for a common rail diesel injector with a varying current wave pattern

A system capable of measuring the time-resolved fuel injection rate of an injector with a varying current pattern supplied to the injector was constructed. The control of the driving of a common rail diesel injector is achieved by controlling the current waveform supplied to the injector. In order to control various current waveforms flowing in the common rail injector, 80 V of power supplied to the injector was switched using a negative-positive-negative (NPN) 2N3055 transistor. The transistor-transistor logic (TTL) switching signal supplied to the base terminal of the NPN 2N3055 transistor was generated from the capture compare PWM (CCP) terminal of a microcontroller. The PWM signal generated from the CCP pin creates five patterns of waveforms by combining the peak-and-hold conditions. In the first part of the 1ms injection period, the duty ratio is 100 %, while the remaining part has a waveform with a greatly reduced duty ratio. The duty ratio used in this study was 10 % or 30 %. The time-resolved pressure wave caused by fuel injection in the Bosch method was repeatedly measured. For an uncertainty analysis, 39 repetitive measurements were taken per fuel injection condition. The rail pressures used in this study were 80, 110 and 140 MPa. With five pick-and-hold current waves supplied to the injector under a rail pressure condition, the time-resolved pressure waves caused by the fuel injection tended to be almost equal during the peak duration, whereas those during the hold duration differed. The duration of the pressure wave caused by the fuel injection is prolonged at a high hold current. When the common rail pressure is high, the slope of the pressure wave in the pick interval is steeper. A parameter that can effectively evaluate the optimal current control pattern for lower power consumption and thermal dissipation of the injector solenoid is also presented.