Transistor Logic Research Articles

Row Hammering Mitigation Using Metal Nanowire in Saddle Fin DRAM

In this article, we investigate a novel technique to minimize row hammer (RH) fail in the saddle fin recessed channel access transistor (S-RCAT) at 1X dynamic random access memory node. We propose a selective introduction of a low work function (WF) metal nanowire (MNW) at the gate metal/gate oxide (GOX) interface to mitigate the RH fail. Using 3-D TCAD simulations, we analyze the mechanism of the RH fail and its mitigation through the use of MNW. The improvement in RH fail is shown due to the MNW and gate-metal work-function-difference induced energy valleys (EVs) between the neighboring S-RCATs. These valleys prevent the diffusion of electrons from aggressor (accessed) to victim (not accessed) cell, which improves RH fail even in the presence of a high concentration of interface states and gate-induced-drain leakage. The introduction of MNW is found not to have any substantial effect on S-RCAT characteristics ( ${V}_{T}$ , ${I}_{ \mathrm{\scriptscriptstyle ON}}$ , or SS). Furthermore, we model the induced EV by considering the WF difference between MNW and gate metal as an effective charge. This model is shown to be in good agreement with the TCAD results. The results obtained in this study demonstrate the potential of using MNW in the gate-stack of S-RCAT for the elimination of RH fail in 1X technology nodes. This technique can also be extended for the use in other device technologies, such as NAND (cell-to-cell interference) and logic transistors.

High‐speed, low power, and dead zone improved phase frequency detector

Design of a novel phase frequency detector (PFD) has been presented here. The innovative advantage of the proposed structure is its improved dead zone performance due to the architectural simplicity which is a combination of static and pass transistor logic (PTL)-based latch configuration. Due to low latency from inputs to the outputs, the operating frequency of the proposed circuit is high while its power consumption is very low. Analytics along with simulations have confirmed the correct behaviour of the designed circuit. For better evaluation of designed architecture advantages, two of the last reported works have been redesigned and simulated along with the proposed PFD. The post-layout simulation results using HSPICE with TSMC 0.18 µm CMOS technology and 1.8 V power supply demonstrate the operating frequency of 1 GHz for the designed circuitry while the power dissipation is 277 µW and the measured dead zone is π / 11 as an enormous enhancement over previous works.

Implementation of Low Power High Speed Adder’s using GDI Logic

Addition is a vital arithmetic operation and is the base of other arithmetic operations such as multiplication, subtraction and division. Adder is a digital circuit that does addition of binary numbers. The 1-bit full adder is the basic block of an arithmetic unit. In VLSI, there are many efficient techniques to design digital circuits. Some of the techniques are Pass Transistor logic (PTL), Complementary metal oxide semiconductor (CMOS) and Transmitter gate (TG). There are several adder designs implemented to reduce the power. However, each design undergoes from precise disadvantage. The adder design with good driving capability requires more power and the design with more delay which consumes less power. In this paper 8-bit Carry Increment Adder (CIA), Carry Bypass Adder (CBA), Carry Skip Adder (CSKA), Carry Look Ahead Adder (CLA), Kogge Stone Adder (KSA), Han Carlson Adder (HCA), and Brent Kung Adder (BKA) are implemented using Gate Diffusion Input (GDI) logic. These designs are simulated and implemented using Tanner tool. The result shows that CBA, CLA, and KSA designs using GDI logic are more efficient compared to CMOS logic in view of power consumption, delay, and area (transistors count) respectively.

Symmetric Stacking Based Fast Binary Counter Using Modified Gate Diffusion Input (M-GDI) Technique

In this paper, modified-Gate Diffusion Input (M-GDI) based binary counter is designed using symmetric stacking method. The binary counter is designed using 3-bit stacker circuit that groups the one bit together and symmetric method is used to form 6-bit stack. The 6-bit stack is converted to binary count to produce required counters. The M-GDI is used to further reduce the transistor count than the CMOS logic transistor count. Mainly the basic gates are developed using the M-GDI technique and the basic gates are replaced in the 6:3 counters to further improve counter-performance. The proposed 6:3 binary counter has no Exclusive or gate (XOR) gates on the critical path, which leads to faster performance of the circuit. The proposed counter is faster, also consumes less power than the traditional. By using this proposed counter in Wallace multiplier, the delay and power for higher-order multipliers is reduced. This paper proposes a novel symmetric stacking based fast binary counters using the modified gate diffusion input (M-GDI) technique. This paper proposes a novel binary counter.

Selective Wet Etching of Silicon Germanium in Composite Vertical Nanowires.

Silicon germanium (SixGe1-x or SiGe) is an important semiconductor material for the fabrication of nanowire-based gate-all-around transistors in the next-generation logic and memory devices. During the fabrication process, SiGe can be used either as a sacrificial layer to form suspended horizontal Si nanowires or, because of its higher carrier mobility, as a possible channel material that replaces Si in both horizontal and vertical nanowires. In both cases, there is a pressing need to understand and develop nanoscale etching processes that enable controlled and selective removal of SiGe with respect to Si. Here, we developed and tested solution-based selective etching processes for SiGe in composite (SiNx/Si0.75Ge0.25/Si) vertical nanowires. The etching solutions were formed by mixing acetic acid (CH3COOH), hydrogen peroxide (H2O2), and hydrofluoric acid (HF). Here, CH3COOH and H2O2react to form highly oxidizing peracetic acid (PAA orCH3 CO3H). The hydrofluoric acid serves both as a catalyst for PAA formation and as an etchant for oxidized SiGe. Our study shows that an increase in anyofthe two oxidizer(H2O2 and PAA)concentrations increases the etch rate, and the fastest etch rate of SiGe is associated with the highest PAA concentration. Moreover, using in situ liquid-phase TEM imaging, we tested the stability of nanowires during wet etching and identified the SiGe/Si interfaceto be the weakest plane; we found that once the diameter of the 160-nm-tall Si0.75Ge0.25 nanowire reaches ∼15 nm during the etching, the nanowire breaks at or very close to this interface. Our study provides important insight into the details of the nanoscale wet etching of SiGe and some of the associated failure modes that are becoming extremely relevant for the fabrication processes as the size of the transistors shrink with every new device generation.

Reducing the power consumption of two-dimensional logic transistors

The growing demand for high-performance logic transistors has driven the exponential rise in chip integration, while the transistors have been rapidly scaling down to sub-10 nm. The increasing leakage current and subthreshold slope (SS) induced by short channel effect (SCE) result in extra heat dissipation during device operation. The performance of electronic devices based on two-dimensional (2D) semiconductors such as the transition metal dichalcogenides (TMDC) can significantly reduce power consumption, benefiting from atomically thin thickness. Here, we discuss the progress of dielectric integration of 2D metal–oxide–semiconductor field effect transistors (MOSFETs) and 2D negative capacitance field effect transistors (NCFETs), outlining their potential in low-power applications as a technological option beyond scaled logic switches. Above all, we show our perspective at 2D low-power logic transistors, including the ultra-thin equivalent oxide thickness (EOT), reducing density of interface trap, reliability, operation speed etc. of 2D MOSFETs and NCFETs.

Study on La2O3 Wet Clean by pH Controlled Functional Water

Introduction For the dimensional scaling and performance enhancement of upcoming semiconductor devices, some novel materials have been implemented. In the high-k metal gate (HKMG) of logic and memory periphery transistors, some lanthanides and alkaline earth metal or their oxides, e.g. lanthanum oxide (La2O3) and magnesium oxide (MgO), have been proposed as a zero-thickness work function shifter [1-7]. These dielectric films are typically patterned by wet processing to enable a multiple threshold voltage [6,7]. However, the wet processes on the new materials are challenging because they dissolve easily in de-ionized wafer (DIW). In this paper, the impact of functional water rinsing on the dissolution and passivation of La2O3 films have been investigated. Experimental detail Coupon testFirst, the effect of etching due to pH was tested. The pH of the solution was adjusted by ammonia or hydrochloric acid. Moreover, O3, H2, H2O2 was added to the ammonia water which dissolution suppression has confirmed, and the effects of their solutions were tested.(2) Wafer test We tested using 10 mm × 10 mm coupon which was cut from 300 mm La2O3 wafers. And the La2O3 coupon was immersed in various dilute solutions under open air conditions. After immersion, the La concentration in the solution was analyzed by ICP-MS. And we calculated the La dissolution amount from these results. The DIW and some functional waters, e.g. CO2 dissolved water (CO2Water), ultra-diluted NH4OH (NH4OH water) , ultra-diluted NH4OH and ultra-diluted H2O2 (NH4OH/H2O2 water), were prepared by using a Kurita functional water unit (HS-13, Kurita Water Industries), which has the capability of injection and mixing CO2 (1 – 40 ppm) and NH4OH (1 – 100 ppm). The 300 mm blanket La2O­3 wafers were processed on a single wafer wet cleaning tool (SU-3200, SCREEN Semiconductor Solutions) connected with the functional water unit. First, We had cleaning tests using CO2 water, DIW, NH4OH water, NH4OH/H2O2 water. Moreover, in order to clarify the dissolution suppression mechanism, the wafer surfaces after cleaning with each solution were analyzed by XRR. Results and discussion Coupon test La2O3 + 6H+ → 2La3 + +3H2O (1).La2O3 + 3H2O → 2La(OH)3 (2).In addition, when H2, O3 and H2O2 were added to ammonia water of pH 10.4, Suppression effects were confirmed by H2O2 added, but we did not have the effect by H2 and O3 gases added(2) Wafer test Several functional waters have been evaluated for the introduction of novel materials and applications for leading edge semiconductor device manufacturing. In case HKMG patterning is required to remove La2O3, CO2W rinsing is preferred. Meantime, NH4OH water and NH4OH/H2O2 water rinsing could preserve the La2O3 layer. Conclusions Cleaning test was performed on a 300 mm La2O3 wafer and the dissolution rate was calculated by performing wafer weight change. Figure 3 shows the etching behavior of La2O3 films treated by DIW, CO2water and NH4OH water and NH4OH/H2O2 water. The results show that the La2O3 film dissolves in CO2water and DIW, of which the pH is acidic or neutral. And XRR measurement ressults are Figure 4, It was suggested that the La2O3 surface after various rinse reatments was formed of La (OH)3. The La (OH) 3 film is thicker by the NH4OH water and NH4OH/H2O2 water cleaning than in the DIW only cleaning. Therefore, it is considered that passivation with a hydroxide film is generated and dissolution is suppressed by setting it as an alkaline region. Regarding the RMG La2O3 patterning for the PMOS devices, it would be required to remove La2O3. Meantime, the La2O3 layer should be preserved for the NMOS devices [6]. Relevant wet etching and rinsing solutions should be used for each patterning step.On the other hand, the dissolution of La2O3 is drastically suppressed in NH4OH water, which is an alkaline solution. Therefore, the La2O3 surface would be passivated by its hydroxide:The results show that La2O3 have following reaction in acidic or neutral solution:Figure 1 is shown that the influence pH on the etching rate of La2O3. By the coupon test, we clarified that the dissolution of La2O3 can be suppressed by raising pH. From this test, it was found that the etching amount was sharply reduced from about pH 1.2 to about 8, and was hardly dissolved over pH 10. Figure 1

Power Analysis of Digital Circuits for VLSI Applications

In this modern world, power plays a very important role in designing of electronic circuits. Portable devices like mobile phones, laptops require electronic circuits that consume less power. Power dissipation causes invariably rise in temperature of electronic circuits. As the temperature increases, the power gets dissipated more. MTCMOS (Multi-Threshold Complementary Metal Oxide semiconductor) power gating is a design technique that reduces power dissipation. It results in the prevention of sub-threshold leakage in standby mode and high speed operation with low power consumption in active mode. In this paper, MTCMOS based MUX is designed and is compared with CMOS MUX and PTL (Pass Transistor Logic) based MUX. It has been concluded that MTCMOS based MUX consumes 16.56% and 15.19% less power than CMOS MUX and PTL MUX respectively. Results are simulated in Mentor Graphics version 10.2.

Design of FinFET-based Energy Efficient Pass-Transistor Adiabatic Logic for ultra-low power applications

This paper presents FinFET-based Energy Efficient Pass Transistor Adiabatic Logic (EEPAL) powered by four-phase power clock capable of operating up to 1 GHz with low energy dissipation. Differential cascode adiabatic logic and pass transistor structure are employed. Furthermore, EEPAL employs discharge transistors assisting in eliminating floating output nodal issues of existing adiabatic circuits. Its efficiency is proved through half and full adder circuits constructed using FinFET-based 2N2P, 2N2N2P, Positive Feedback Adiabatic Logic (PFAL), Differential Cascode Pre-resolve Adiabatic Logic (DCPAL) and Pass transistor Adiabatic Logic (PAL) based circuits. Carry Lookahead Adder (CLA) and Carry Save Multiplier (CSM) are used as benchmark circuits to validate the efficiency of EEPAL. Energetics of EEPAL and effect of parameter variations on energy dissipation have been derived and analyzed. BSIMCMG FinFET models have been used for simulations in Cadence® Virtuoso. At 500 MHz, 16-bit CSM designed using EEPAL is 25%, 34%, 21% and 12% energy efficient than CSM designed using 2N2P, 2N2N2P, PFAL and DCPAL.

3D Double-Gate Junctionless Nanowire Transistor-Based Pass Transistor Logic Circuits for Digital Applications

We investigate the circuit performance of the junctionless nanowire transistor. We have demonstrated pass transistor-based logic gates using the junctionless transistor. Pass transistor-based basic logic gates: AND, OR, XOR are designed using only the n-type junctionless nanowire transistor with HfO2 gate dielectric. Simulations of these circuits have been studied and analyzed under a mixed-mode environment. Outcomes of the analysis show that 3D dual gate junctionless nanowire transistor with 20 nm gate length well performed for pass transistor logic. In addition, a junctionless nanowire transistor-made multiplexer has also been studied and found to perform well. A high-k gate dielectric was used for all junctionless transistors as the higher k value improves the device characteristics and circuit performances. Our study also shows that the junctionless nanowire transistor-based pass transistor logics for digital circuit perform well.

Energy Efficient SRAM

Memories are an essential unit of any digital circuit, thus their power consumption must be considered during the designing process of the cells. To improve performance, reduce delay and increase stability, it is advisable to decrease the power consumed by the memory. Due to high demand of speed, high performance, there’s a need to decrease the size of the device, thereby increasing the devices placed per chip. This high integration makes chips more complex but improves device performance. Design of SRAM cells with speed and low power is crucial so as to replace DRAMs. The layout of SRAM has advanced to meet the requirements of the present industry in accordance with parameters like delay, power consumption and stability etc. This paper presents the aim of analyzing different technologies used to make SRAM more efficient in terms of parameters such as static noise margin, latency and dissipation of power. The stability investigation of SRAM cells are usually derived from the Static Noise Margin (SNM) analysis. Here we observe a SRAM design which has used dynamic logic and pass transistor logic. We further study the effects made on this design by employing various technologies such as AVL-S, AVL-G, AVL and MT-CMOS, at 180nm CMOS technology to achieve enhancements in delay, power consumption and performance. The proposed circuits are simulated and the results obtained have been analyzed to show significant improvement over conventional SRAM designs. Cadence Virtuoso simulation is used to confirm all the results obtained in this paper for the simulation of 180 nm CMOS technology SRAMs.

Performance Analysis of Inductive Source Degeneration Low Noise Amplifier using Multi-finger Technique

In the current paper, common source Low Noise Amplifier using inductively degenerated technique is designed to meet Radio Frequency (RF) range 2.45 GHz-2.85 GHz. The designed LNA is implemented using single and multi-finger transistor logic. The transistor geometry greater than 300 μm has been split into multiple fingers using multi-finger technology. The schematic is captured using ADS. The performance of LNA for various technologies has been analyzed using PTM 180 nm, PTM 130 nm and PTM 90 nm models. The amplifier with single transistor achieves minimum noise figure of 0.178 dB noise figure and maximum gain of 20.045 dB using 130 nm model technology for Bluetooth applications. Similarly 0.288 dB of minimum noise figure and peak gain of 17.971 dB are obtained using multi-finger MOSFET of PTM 90 nm technologyrespectively.The reverse isolation (S12) below -50 dB is achieved.

Design and Implementation of High Performance and Low Power Mixed Logic Line Decoders

The decoders are widely used in the logical circuits, data transfer circuits and analog to digital conversions. A mixed logic design methods for the line decoders are used to combining the transmission gate logic, pass transistor logic, and complementary metal-oxide semiconductor (CMOS) technology provides desired operation and performance. A novel topology is presented for the 2 to 4 decoder requires a fourteen transistor topology aiming on reducing the transistor count and operating power and a fifteen transistor topology aiming on high power and low delay performance. The standard and inverting decoders are designed in each of the case, gives a total of four new designs circuits. All the proposed decoders have compact transistor count compared to their conservative CMOS technologies. Finally, a variety of proposed designs present a noteworthy improvement in operating power and propagation delay, outperforming CMOS in almost all the cases.

A Monolithic 500°C D-Flip Flop Realized in Bipolar 4H-SiC TTL Technology

This work presents the design, in-house fabrication, and electrical characterization of a monolithic medium scale integrated (MSI) D-type flip-flop (DFF). It consists of 65 n-p-n bipolar transistors and 49 integrated resistors. The monolithic bipolar DFF is realized using basic gates by employing the structured way of implementation, whereas the basic gates are implemented by employing the conventional transistor-transistor logic (TTL). The positive-edge-triggered DFF, with synchronous active-low reset is characterized in the temperature range of 25-500 °C. The circuit has been tested in two modes of operation; data input mode and clock divider. Non-monotonous temperature dependence is observed for the flip-flop propagation-delay clock-to-output (tPCQ), rise-time and fall-time; decreases with the temperature in the range 25 °C to 300 °C, while it increases in the range 300 °C to 500 °C. The transient response has also been measured at a clock frequency of 100 kHz. At T = 400 °C and VCC = 15 V, the DFF consumes minimum energy ≈ 234 nJ.

FPGA-based real-time autocorrelator and its application in dynamic light scattering

Digital correlators play a significant role in dynamic light scattering (DLS) technology, which characterizes particle size distribution. We present a field programable gate array (FPGA)-based digital correlator that can be applied to process DLS data. To satisfy the DLS requirements in the FPGA logic with limited resources, a multiple lag time period (multi-τ) method is employed that does not require storing the full dataset in memory. Moreover, the device directly accepts the transistor–transistor logic (TTL) signal from the photon counting detector by measuring the time intervals between photon events and calculates the autocorrelation functions in real time. Furthermore, we derive estimates for the error arising from the use of the multi-correlator. We implement all the necessary operations in a single Xilinx FPGA chip with a lag time from 10 ns to 45 min, including a highly optimized photon counter.

Design Optimization and Modeling of Charge Trap Transistors (CTTs) in 14 nm FinFET Technologies

The Charge Trap Transistor (CTT) technology is an emerging memory solution that turns as-fabricated high- ${k}$ /metal gate (HKMG) logic transistors into secure, embedded non-volatile memory (eNVM) elements with excellent data retention and operation capability at military grade temperatures. In other words, the CTTs offer a completely process-free and mask-free eNVM solution for advanced HKMG CMOS technology nodes. In this letter, bitcell design to enhance programming efficiency and modeling of the charge trapping behavior of CTTs in 14 nm FinFET technology is discussed.

Non‐contact method based on intensity modulation of light for measurement of vibration of a thin cantilever beam

A non-contact method based on intensity modulation of light for measurement of vibration of a thin cantilever beam (CB) is presented in this study. The system consists of a laser source, a photo-detector-based signal conditioning and comparator circuit, an ATmega8 microcontroller based data acquisition system and an interface with personal computer. The sensing principle is based on modulation of intensity of light falling laterally on a vibrating CB. The photo-detector detects the modulated light and generates pulses, which is processed by signal conditioning and comparator circuit. The output of the comparator consists of alternative high and low transistor–transistor logic pulses, interfaced to two pins of the microcontroller simultaneously; one to external event counter and the other to input wave capture. The microcontroller is used to measure the frequency, width of high and low pulses. The system is calibrated using a Tektronix AFG3251C Arbitrary Function Generator. The % error in measurement of width of pulses is found to be within the range +0.12 to −0.41%, whereas 0% measurement error is observed in the measurement of frequency. Experimental results obtained under free vibration tests of two samples of thin CB of 0.4 and 0.5 mm thickness are also presented.

A Variation-Aware Robust Gated Flip-Flop for Power-Constrained FSM Application

Advancement in technology towards mobile computing and communication demands longer battery life, which mandates the low power design methodologies. In this paper, we have presented a novel low-power 8T flip-flop (FF) architecture, which has outsmarted the existing well-known dynamic, semi-dynamic and explicit pulsed flip-flops in terms of power and delay. The major ingredient of this architecture is a voltage keeper, which is incorporated to achieve reliable logic switching at the propagating nodes of the design. However, we have also come up with two new approaches of gated clock generation based on transmission gate (TG) and pass transistor logic (PTL) as a modification of LECTOR-based gating. These gating logics have proved themselves to be competent enough to reduce both the static and dynamic power dissipations and hence are employed to the proposed flip-flop to achieve further reduction in power than its nongated correspondent. The performance of this proposed gated flip-flop is tested in a finite state machine with its application in low-power serial adder design. All the simulations are carried out using 65-nm and 90-nm CMOS technologies with a power supply of 1.1[Formula: see text]V at 6.6[Formula: see text]GHz clock frequency. The gated FF saves 52.12%, 6.36% and 28.18% average power-using LECTOR, TG and PTLs, respectively, with respect to its nongated counterpart in 65-nm technology. The performance metrics of gated and nongated proposed designs are affirmed in the environment of commercialized CMOS foundry.

Theory of Expansion Boolean Algebra and Its Applications in CMOS VLSI Digital Systems

Based on the relationship between circuits (systems) and the signals in the circuits (systems), the theory of expansion Boolean algebra is presented in this paper. Static complementary logic circuits and static pass transistors logic circuits have been used to implement the high-speed and low-power-consumption cells circuits in CMOS VLSI systems. It is important to study the extraction method of logic expressions for these types of circuits. By analyzing the operations principles of MOS transistors in CMOS circuits, the theory of expansion Boolean algebra of CMOS logical circuits is presented. Based on the algebraic theory, a method of extracting the logic expressions from the two types of CMOS logical circuits is derived. On the basis of the method, a switch-level design method of CMOS logic circuits based on the algebra theory is presented, and the design method is used to design the high-speed and low-power full adder cells in CMOS VLSI systems. By the results of the simulation experiments, it is shown that the pass transistors and transmission gates hybrid CMOS full adder circuits proposed in this paper have a lower power-delay product by comparison with the full adder circuits designed by using other methods.

Noise Synthesis Technique in Time Domain for Metrology Application

We developed a prototype radiometer system to implement a time-domain noise synthesis technique. A solid-state (SS) switch synthesizes noise signals from the outputs of two synchronized electromechanical (EM) switches. The input ports of EM switches are terminated by one unknown noise source, one known cold noise reference, and two known ambient noise references. The magnitude of the synthesized noise signals can be varied by the duty cycle of the transistor–transistor logic (TTL) pulse that controls the SS switch. By regulating the TTL pulse, a null balance is reached when the power level of the synthesized noise signals equal to that of the ambient noise reference. The noise synthesis radiometer represents a major step forward over the conventional noise-injection radiometer, enabling highly efficient measurements of the noise temperature with improved precision. The uncertainty due to nonidentical input-impedance states is also properly accounted for. Several future works are suggested to further improve the system performance.