Design and comparative analysis of D-Flip-flop using conditional pass transistor logic for high-performance with low-power systems

Abstract

Flip-flop is one of the essential elements of data path structure design in the digital era. In this paper, the peculiar Flip-flop topologies, called as Conditional Pass Logic Static D-Flip-Flop (CPLSDFF) and Conditional Pass Logic Dynamic D-Flip-Flop (CPLDDFF) are proposed. The main objective of the proposed system is to optimize the primary performance criterions such as area and power. The first parameter is attained by reducing the device count, and the later is achieved by removing the redundant transistor switching, charge sharing and frequent power consumption from the source. The CPLSDFF and CPLDDFF are designed using SPICE with 130 nm IBM transistor technology and it shows that the silicon area is reduced up to 27% and 22% respectively. The conditional pass-transistor logic method is introduced in the proposed system leads to minimizing the unnecessary switching activity, charge sharing in intermediate nodes and power utilization is also minimized up to 12% in the static model, 70% in the dynamic model. The various performance parameters like transistor count, the clock driving power, data driving power, switching activity and propagation delay (D-Q) of the Flip-flop are investigated in detail and are correlated with the existing designs. The optimized CPLFF structures are also employed in 8-bit serial in serial out (SISO) shift registers and can save power up to 35% and 42% respectively. The outcomes show that the proposed system is most adaptable for low power applications with superior performance in register designs.