Length Transistors Research Articles

Area-efficient all-digital pulse-shrinking smart temperature sensor with improved accuracy and resolution.

An all-digital CMOS (Complementary Metal-Oxide Semiconductor) pulse-shrinking smart temperature sensor (PSSTS) is proposed to deliver the merits of area efficiency, improved accuracy, and high resolution. First, an inverter-based temperature-sensing delay line generates a pulse with a width proportional to absolute temperature (PTAT). Then, a pulse-shrinking delay line (PSDL) with a pulse-mixing scheme (PMS) measures the PTAT pulse through pulse shrinking. The two delay lines become area efficient when the channel length of transistors is long. Conventionally, the area-efficient PSDL decreases the time resolution. Thus, the all-digital PMS considerably enhances the time resolution and achieves an excellent sensor resolution. Finally, a time subtractor improves sensor accuracy by effectively eliminating the offset error effects. The proposed sensor was implemented in a Taiwan Semiconductor Manufacturing Company 0.35-μm CMOS process and occupied an area of 0.0247 mm2, which is the best area among related studies. The PSSTS exhibited an improved inaccuracy from a maximal inaccuracy of 1.95 °C to 1.5 °C and an excellent resolution of approximately 0.05 °C/LSB. Experimental results prove that this study is area-efficient and achieves improved accuracy and high resolution.

Physical insights into the operation of a 1-nm gate length transistor based on MoS2 with metallic carbon nanotube gate

Low-dimensional materials such as layered semiconductors or carbon nanotubes (CNTs) have been attracting increasing attention in the last few decades due to their inherent scaling properties, which become fundamental to sustain the scaling in electronic devices. Inspired by recent experimental results [Desai et al., Science 354, 99 (2016)], in this work we examined the ultimate performance of MoS2-channel Field Effect Transistors with a gate length of 1 nm by means of quantum transport simulations based on the Poisson equation and non-equilibrium Green's function formalism. We considered uniformly scaled devices, with channel lengths ranging from 5 to 20 nm controlled by a cylindrical gate with a diameter of 1 nm, as would be required in realistic integrated circuits. Moreover, we also evaluated the effect of the finite density of states of a carbon nanotube gate on the loss of device performance. We noticed that the sub-threshold swing for all short-channel structures was greater than the ideal 60 mV per decade limit of thermionic devices, and we attributed this to the presence of tunneling currents and gate-drain interactions. We tailored the transistor architecture in order to improve the gate control. We concluded that the limited CNT-channel capacitive coupling poses severe limitations on the operation and thus exploitation of the device.

Power Optimization in System Level Using Profiling Technique

Power optimization has become an essential and major source of concern at the system level design. With the shrink in transistor length and the attractiveness of handy electronic devices, power dissipation has become a serious issue. System level power optimization technique gains more popularity since many techniques can be applied in reduction of power. Although, there are numerous techniques to reduce power dissipation, simpler methods has not been implemented on a system level. In this paper we use profiling technique, a process which helps one to know which portion of the function takes more time compared to other during the simulation. The portion which takes large time for simulation is port mapped to the FPGA while the rest is assigned to the processor. By this technique we can see considerable amount of power savings.

Low power and high speed design issues of CMOS Hamming code generation and error detection circuit at 22 nm and 16 nm channel length of MOS transistor

This paper represents low power and high speed design issues of Hamming code generation and error detection circuit using complementary metal oxide semiconductor (CMOS) technology. Average power consumption and input to output gate delay for both Hamming code generation and error detection circuit are analyzed at 22 nm and 16 nm channel length of Metal Oxide Semiconductor (MOS) transistor. The functionality of the circuits are clarified using Tanner SPICE (T-SPICE) software. The average power consumption and input to output gate delay of the circuits are reported considering the parameters—power supply voltage, channel width to length ratio of transistors. It has been observed that whenever power supply voltage (VDD) increases, power consumption across the circuits increases, however gate delay decreases for both the circuit for fixed channel width to length ratio of the transistors. On the other hand, for fixed value of VDD if channel width to length ratio of NMOS transistor increases gate delay decreases however average power consumption increases. The variation of average power consumption and delay has also been reported with respect to KPN ratio. KPN is the ratio of channel width to length ratio of PMOS transistor to channel width to length ratio of NMOS transistor. Average power consumption is more for higher value of KPN ratio. In contrast gate delay is less at higher value KPN ratio. In this work, the values of average power consumption and gate delay are of the order of microwatt and picosecond respectively. The average power consumption of the Hamming code generation circuit in this work at 0.8 V of VDD is 0.2 µW and 1.3 µW for 22 nm and 16 nm cannel length of MOS transistor respectively. Whereas at the VDD of 0.8 V, the average power consumption of the error detection circuit is 0.4 µW and 2.3 µW respectively for 22 nm and 16 nm cannel length. The gate delay of the Hamming code generation circuit in this work at VDD of 0.8 V is 4.7 ps and 3.3 ps for for 22 nm and 16 nm cannel length of MOS transistor respectively. Also at the VDD of 0.8 V, the gate delay of the error detection circuit has been reported in this work is 16.4 ps and 12.5 ps for 22 nm and 16 nm channel length respectively. Therefore for low power and high speed Very Large Scale Integrated (VLSI) circuit design this work is applicable.

Static noise margin trade-offs for 6T-SRAM cell sizing in 28 nm UTBB FD-SOI CMOS technology

In this paper, analytical expressions for the conventional definition of write static noise margin (WSNM) for 6T-SRAM cells at sub-threshold operation are derived. Drain-induced barrier lowering (DIBL) and body-biasing effects are considered in order to achieve an appropriate model for fully depleted silicon-on-insulator (FD-SOI) CMOS technology. By observing the expressions for WSNM and read SNM (RSNM) we introduce an alternative design parameter (Γ) for 6T-SRAM cell sizing, whose purpose is to control read and write static noise margins simultaneously, thereby providing effective stability balance. This paper also shows that low-leakage cells with suitable stability can be designed by using a non-traditional sizing for 6T-SRAM cells, in which increased transistor lengths are employed to reduce leakage, assisted by a word-line voltage reduction technique to increase read margin. In addition, a statistical analysis for both read and write static noise margins taking into account manufacturing process variations was carried out with the purpose of designing a high-yield 6T cell. Analytical expressions and the designed 6T cell were verified by extensive HSPICE simulations using a 28 nm ultra-thin body and buried oxide (UTBB) FD-SOI CMOS technology.

Alternative Spin-On-Glass (SoG) material characterization For Deep-Submicron (

Currently a submicron soft reflow process developed in University of Manchester uses silicon nitride (Si3N4) as the hard mask layer to support the T-Gate structure of pHEMTs in order to make it mechanically stable. However, an alternative material known as Spin-on-Glass (SoG) is introduced to replace Si3N4, offering shorter processing time and consequently, a much simpler and more cost-effective alternative to the e-beam lithography of nanometre-scale gate length transistors. The SoG deposition through plasma-enhanced chemical vapour deposition process requires only 30 minutes to complete, as opposed to the one-day process of depositing Si3N4. In this study, the SoG material used is Silicafilm, and the minimum deposition thickness achieved is 138 nm, enabling 150-nm gate length devices to be fabricated. The SoG is also successfully etched at very low power and pressure (20 W and < 25 mTorr respectively), eliminating the detrimental effect of high power plasma etching to the 2DEG carriers. In addition to that, no film cracks observed even by using a single coating and a single baking temperature of 200 °C. All these results indicate the potential of SoG as a suitable hard mask layer alternative to the silicon nitride for the use soft reflow fabrication process.

Temperature Sensitivity based on Channel Length of FinFET Transistor

This paper presents the temperature sensitivity of the gate length-based fin field effect transistor (FinFET) and the possibility of using such a transistor as a nano-temperature sensor. The multi-gate field effect transistor (MuGFET) simulation tool is used to investigate the temperature characteristics of FinFET. Current–voltage characteristics with different temperatures and gate lengths (Lg = 25, 45, 65, 85 and 105 nm) are initially simulated, then the metal oxide semiconductor diode mode connection to measure FinFET temperature sensitivity is considered. The best temperature sensitivity of the FinFET is observed on the basis of the largest ΔI at the working voltage VDD range of 0–5 V. Furthermore, temperature sensitivity of the FinFET increased linearly with channel length at the range of 25–105 nm.

Variability in Output Characteristics of Single-Walled Carbon Nanotube Thin-Film Transistors

Single-walled carbon nanotube (CNT) based thin-film transistors (TFTs) are promising candidates for future electronic devices because of their excellent properties. However, device-to-device performance variability of TFTs can pose challenging problems, which is rooted in the randomness of CNT networks, the variation in individual CNT properties due to change in chirality, and the fabrication imperfections. This paper presents a systematic study of variability in I-V characteristics through a combination of experimental and theoretical analysis of the major sources that cause performance variation. The sources of variation including the percentage of metallic CNTs (m-CNTs), threshold voltage, CNT mean length, and CNT network density have been studied separately. The analysis shows that the presence of m-CNTs is a major source contributing to the performance variation for short channel TFTs, but its effect reduces for large channel length transistors. The threshold voltage is found to be the major source of variation for long channel TFTs. A better consistency in performance can be guaranteed for TFTs with larger channel area, which ensures a smaller variation in CNT network density and CNT mean length. These results provide key insights into the variability estimation of I-V characteristics of CNT-based devices, which is vital for reliability studies of CNT-TFTs based circuits for different electronic applications.

Sub-THz Imaging Using Non-Resonant HEMT Detectors

Plasma waves in gated 2-D systems can be used to efficiently detect THz electromagnetic radiation. Solid-state plasma wave-based sensors can be used as detectors in THz imaging systems. An experimental study of the sub-THz response of II-gate strained-Si Schottky-gated MODFETs (Modulation-doped Field-Effect Transistor) was performed. The response of the strained-Si MODFET has been characterized at two frequencies: 150 and 300 GHz: The DC drain-to-source voltage transducing the THz radiation (photovoltaic mode) of 250-nm gate length transistors exhibited a non-resonant response that agrees with theoretical models and physics-based simulations of the electrical response of the transistor. When imposing a weak source-to-drain current of 5 μA, a substantial increase of the photoresponse was found. This increase is translated into an enhancement of the responsivity by one order of magnitude as compared to the photovoltaic mode, while the NEP (Noise Equivalent Power) is reduced in the subthreshold region. Strained-Si MODFETs demonstrated an excellent performance as detectors in THz imaging.

Experimental ${g}_{m}/{I}_{{D}}$ Invariance Assessment for Asymmetric Double-Gate FDSOI MOSFET

Transconductance efficiency ( ${g}_{m}/{I}_{D}$ ) is an essential design synthesis tool for low-power analog and RF applications. In this paper, the invariance of ${g}_{m}/{I}_{D}$ versus normalized drain current curve is analyzed in an asymmetric double-gate (DG) fully depleted MOSFET. This paper studies the breakdown of this invariance versus back-gate voltage, transistor length, temperature, drain-to-source voltage, and process variations. The unforeseeable invariance is emphasized by measurements of a commercial 28-nm ultrathin body and box fully depleted Silicon-on-Insulator (SOI) (FDSOI) CMOS technology, thus supporting the ${g}_{m}/{I}_{D}$ -based design methodologies usage in DG FDSOI transistors sizing.

Automated sizing of low-noise CMOS analog amplifier using ALCPSO optimization algorithm

The main aim of the automated design methodology is to improve the design process in terms of cost, robustness and performance. Presence of noise restricts the minimum level of signal that a circuit can processed with an acceptable quality which increases the complexity of the circuit. Optimization is a time consuming and difficult tasks that involves handling wide variety of conflicting constraints or design specifications and wide range of design parameters. In this paper, Particle Swarm Optimization with an Aging Leader and challengers (ALCPSO)-based design methodology is proposed. ALCPSO is used to search the solution space for computing the constraints and design parameters with main aim of simultaneously minimizing the thermal noise and area of the circuit. In other word, the proposed design methodology incorporate noise as design specification along with other specifications which were lacking in previous automated methodology. And this methodology gives a platform to optimize both length and width of MOS transistor which will further minimize the circuit area. The computation of the ALCPSO-design methodology is performed using MATLAB and is linked to CADENCE tool with 0.18 µm parameters technology to verify the ALCPSO-based design methodology.

Variability aware transistor stack based regression surrogate models for accurate and efficient statistical leakage estimation

In this paper, we present highly accurate and very efficient stack based surrogate models for standby (idle-time) statistical leakage estimation of CMOS circuits using sampling based methods. Our aim is to replace SPICE simulation with our proposed surrogate models, which can be used to evaluate samples generated by sampling methods in variation space. Our methodology initiates by first characterizing the leakage of basic transistor stacks and then provides estimate of the leakage of basic gates based on these stacks. Transistor stacks are extracted across various standard cells, which are used to estimate leakage of CMOS gates with different input vector combinations. We develop Support Vector Machine (SVM) regression surrogate models and characterize the transistor stacks of CMOS gates, while accounting the combined effect of process variations in transistor length (L), threshold voltage (Vth), oxide thickness (Tox), supply voltage (0.6V−1.2V), temperature (0°C−100°C) and width (28nm−200nm), all scalable at the same time. For gates containing parallel transistor stacks, we merge the parallel transistors having identical inputs, which in turn allows us to use precharacterized basic stacks for leakage calculation, thus avoiding generation of new models. Our experiments illustrate that we only require 30 and 26 stack models to predict the subthreshold and gate tunneling leakage of 20 different gates across 176 input combinations, instead of characterizing leakage model for each input vector separately. SVM regression models generated in our approach have the ability to predict the leakage with maximum average error of 2.7% in mean (μ) and maximum average error of 3.1% in standard deviation (σ), both for OAI22 gate. Our results establish that there is on an average 10× improvement in runtime while estimating the μ and σ of leakage of a gate within 10000 Monte Carlo simulation loop. Our approaches also result into a maximum of 221× runtime improvement for C6288 ISCAS'85 benchmark circuit. We further develop Sparse SVM models using Support Vector spectrum pruning method, which reduces the runtime of the regression models with negligible increase in the error. Runtime efficiency of 17× and 323× is achieved on standard cell library and C6288 benchmark circuit respectively using Sparse SVM models. Our models outperform previous models based on analytical equations and Artificial Neural Network in terms of accuracy.

Accurate Modeling of Gate-Induced Drain Leakage for III-V Mosfets

As the channel length of the metal oxide semiconductor field-effect transistors (MOSFESTs) enters into the nanoscale regime, quantum mechanical effects such as carrier confinement, interference effects and tunneling become dominant. Therefore, accurate and efficient device simulation tools based on a quantum mechanical formalism are necessary to interpret experimental results. Among several approaches, the Non-Equilibrium Green’s Function (NEGF) method provides most rigorous framework for treating quantum transport in nanoscale devices. However, a full NEGF treatment can be highly demanding and in some cases almost impossible to implement due to numerical burden. As a concrete example, let us examine Fig. 1. The schematic shows the well-known band diagram for gate induced drain leakage. When the gate voltage is lowered at high drain voltage, a tunneling current can flow from the bulk to the drain through band-to-band tunneling. There are two energy regions of interest: (i)E1; the two ends of which are cut off by the band edges and (ii)E2; which is the region underneath the valence band in the body region but above E1. In a ballistic scenario, the region E2 is devoid of electrons and all the band-to-band current flows in the region E1. This is also what is calculated in NEGF. However, in reality, electron-electron interaction quickly fills up E2 according to the Fermi statistics, and so a tunneling current should also flow in this region.Especially, for direct and low band gap materials such as III-V, this current can be a significant part of the total tunneling current. The problem is that it is numerically extremely challenging, if not impossible, to include electron electron interactions in the NEGF formalism, and therefore to account for the current that flows in E2. To account for this problem, in this work, we have taken a two-pronged approach. First, we show that a Wentzel-Kramers-Brillouin (WKB) approximation calculated using the imaginary part of the full band-structure provides a very close agreement with NEGF results (typically within a few percent). This is especially accurate at low current levels where the Laplace solution of the potential provides a very good estimate for the self-consistent potential of the problem. We then combine this with a mode-space calculation of the currentvoltage characteristics. The mode-space approach is particularly valid when the device is uniform along the transport direction as it is the case for double gate or most of the FinFET structures. The mode space approach demands much smaller numerical burden as each mode is solved independently. This also means that in a standard approach, it cannot account for band-to-band tunneling. Our strategy is to combine the WKB approximation with the mode space approach so that the ordinary current is calculated using the mode space while the band-to-band tunneling current is calculated using WKB. We first show that this combined strategy provides current-voltage characteristics that show excellent agreement with full, real-space, NEGF calculations, including the band-to-band tunneling in the E1 region. We then add the additional current that flows in E2 by assuming a Fermi distribution of the electrons in that region. Our work thus provides a very fast, yet accurate approach to calculate currentvoltage characteristics in direct bandgap semiconductors using the NEGF method. Figure 1

(Invited) Interface Engineering of High-k Dielectrics and Metal Contacts for High Performance Top-Gated MoS2 FETs

The 2D materials, in particular Transition Metals Di-chalcogenides (TMD), are potential candidates to scale CMOS technology beyond Silicon. The ability to deposit ultrathin TMD films, down to a mono-layer, offers excellent electrostatic control of the channel by the gate electrode. This enables aggressive scaling of the channel length of transistor, due to superior short channel performance. In particular, few layer Molybdinum Disulphide (MoS2), with a bandgap comparable to Silicon, has emerged as a promising candidate to to enable continued transistors scaling. However, high performance and reliable gate dielectric and contact formation continues to be an open problem. Since the impurity doping strategies for MoS2 are still not clear, the ohmic contact formation is limited by the nature of metal-semiconductor schottky contact. Despite the Fermi level pinning close to conduction band of MoS2, a low source/drain contact resistance value for NMOS transistor is limited by the surface state effects. The problem is exasperated due to large variations in contact resistance values within the wafer, possibly due to surface defects and stoichiometric variations. We demonstrate that appropriate surface preparation can drastically enhance the performance of ohmic contacts on MoS2. In particular, we present a surface-state engineering technique using sulfur treatment of MoS2 before the contact formation. The transistors (L=W= ~1μm) are formed on exfoliated few layer MoS2 flakes (5-7 nm thick). The flakes are treated with ammonium sulphide solution (NH4)2S (Sigma Aldrich, 40% solution in H2O) for 5 min at a temperature of 50 °C, followed by De-ionized water rinse and N2 blow-dry. Nickel (Ni) and Palladium (Pd) contacts are formed using lift-off process. Through extensive material and electrical characterization, we demonstrate that the sulfur treatment reduces to schottky barrier height by 81 meV (Ni) and 135 meV (Pd) due to stronger pinning of Fermi level. This in turn lowers the contact resistance by as much as 10 times with concomitant increase in mobility by a factor of 2. We demonstrate record drain current of 170μA/μm, with complete mitigation of contact resistance and hence drain current variability. Due to the inert basal plane of 2D materials, it is difficult nucleate the growth of dielectrics using CVD and/or ALD techniques, which are routinely used for high-k dielectric integration on Silicon. Although some techniques have been proposed to nucleate the dielectric growth on MoS2, the device performance is inferior due to interface defects. To circumvent this issue, we develop a very high performance HfO2 thin film using electron beam evaporation. The O2 flow rate is optimized during e-beam evaporation to achieve 30nm HfO2 films with k=19 and EOT=6.1 nm. The interface trap density is estimated to be 8.7x1011 /cm2, resulting in a very high field effect mobility value of 63 cm2/V-s. The HfO2 gate oxide results in a very low leakage current of 7x10-7 A/cm2. The top gated transistors fabricated with this dielectric yield one of the highest reported drain current value of 180 μA/μm, with near ideal subthreshold behaviour (60 to 75 mV/decade). We also utilize 30nm HfO2 dielectric as a substrate to deposit MOS2 flakes, instead of conventional 300nm SiO2 substrate. Finally we demonstrate an NMOS inverter circuit using HfO2 top-gated devices using a depletion mode NMOS transistor as a resistive load. The Inverter exhibits an output to input gain of about 9. Figure 1

Application of Fin Structure Factor to Reduce the Body Effect in 20 nm DRAM Cells

Body effect—a key characteristic of dynamic random access memory (DRAM) cell transistors—is affected by the length and width of conventional planar transistors. However, in buried channel structures developed recently, the fin structure is also known to affect the properties of a transistor. In this paper, the effect of the fin structure on the body effect of a DRAM cell is investigated. In addition, a scheme for reducing this effect is suggested. In order to measure the body effect in a DRAM cell, a nondestructive measurement method was used. This method uses a memory test system for fast, massive, nondestructive measurement. Using the measured data, we compared the body effect and the fin dimension. The results show that there is a strong correlation between the fin height and the body effect.

Monolayer Bismuthene-Metal Contacts: A Theoretical Study.

Bismuthene, a bismuth analogue of graphene, has a moderate band gap, has a high carrier mobility, has a topological nontriviality, has a high stability at room temperature, has an easy transferability, and is very attractive for electronics, optronics, and spintronics. The electrical contact plays a critical role in an actual device. The interfacial properties of monolayer (ML) bismuthene in contact with the metal electrodes spanning a wide work function range in a field-effect transistor configuration are systematically studied for the first time by using both first-principles electronic structure calculations and quantum transport simulations. The ML bismuthene always undergoes metallization upon contact with the six metal electrodes owing to a strong interaction. According to the quantum transport simulations, apparent metal-induced gap states (MIGSs) formed in the semiconductor-metal interface give rise to a strong Fermi-level pinning. As a result, the ML bismuthene forms an n-type Schottky contact with Ir/Ag/Ti electrodes with electron Schottky barrier heights (SBHs) of 0.17, 0.22, and 0.25 eV, respectively, and a p-type Schottky contact with Pt/Al/Au electrodes with hole SBHs of 0.09, 0.16, and 0.38 eV, respectively. The effective channel length of the ML bismuthene transistors is also significantly reduced by the MIGSs. However, the MIGSs are eliminated and the effective channel length is increased when ML graphene is used as an electrode, accompanied by a small hole SBH of 0.06 eV (quasi-Ohmic contact). Hence, an insight is provided into the interfacial properties of the ML bismuthene-metal composite systems and a guidance is provided for the choice of metal electrodes in ML bismuthene devices.

Large-signal distributed millimeter-wave multifinger pHEMT modeling using time-domain technique

The finite-difference time-domain (FDTD) method is used for the large-signal modeling of a multifinger pHEMT, which is considered as five nonlinear coupled distributed transmission lines. The developed model, which is based on the exact physical layout of multifinger pHEMT, not only accurately describes the propagation effects along the electrodes at higher frequencies but it also includes major nonlinearities of the I–V and Q–V characteristics. Using the transmission line theory, a proper nonlinear equivalent lumped circuit model is allocated for the differential length of the quintuple-line transistor and the nonlinear active multiconductor transmission line (NAMCTL) equations are derived. These nonlinear, coupled differential equations are numerically solved using the FDTD method. The proposed model is applied to a 100 nm GaAs pHEMT and the simulation results are compared with the results of conventional sliced model in Keysight ADS simulator. The developed transient nonlinear model accurately predicts both the S-parameters (1–150 GHz) and large-signal power performances especially at millimeter wave frequency range. The proposed model can be useful in design and analysis of various types of high-frequency nonlinear integrated circuits.

Two-dimensional modeling and analysis of a nanometer transistor as a THz emitter

In this paper, we report on the influences of quantum effects, electron exchange-correlation, Fermi velocity, gate to channel distance and viscosity on the plasma frequency and instability of the plasma waves in a nanometer transistor. By extending the analysis to two-dimensional case, allowing oblique wave propagation, including viscosity and departing from gradual channel approximation, we obtain a general analytical expression for dispersion relation, plasma frequency, and “increment.” We found that, while the plasma frequency decreases with the electron exchange-correlation effect, it increases with quantum effects and Fermi velocity. It is shown that the spectrums of plasma waves are discrete both in longitudinal and lateral (transverse) direction. We also express the total radiated power in terms of transistor parameters especially the lateral dimension. Viscosity which is inherently presented in the structure and cannot be neglected, dramatically decrease the emitted power and set a lower limit on the length of transistor. We show that a nanometer transistor with a long width (a long lateral dimension) has advantages for the realization of practical terahertz emitters.

Influence of Chain Length of 1D Thermal Transistor on Thermal Amplification Factor

We study the influence of chain length of our 1D model of thermal transistor on thermal amplification factor. Here, we varied the length of drain and source segments for different simulation experiment and found that the maximum value of thermal amplification factor influenced with chain length. The thermal amplification factor of the thermal transistor is found to be dependent on gate temperature. We also calculated the switching efficiency and working region of the thermal transistor and better results are obtained in comparison to previous study.

Heteroepitaxial growth of In0.30Ga0.70As high-electron mobility transistor on 200 mm silicon substrate using metamorphic graded buffer

We report on the growth of an In0.30Ga0.70As channel high-electron mobility transistor (HEMT) on a 200 mm silicon wafer by metal organic vapor phase epitaxy. By using a 3 μm thick buffer comprising a Ge layer, a GaAs layer and an InAlAs compositionally graded strain relaxing buffer, we achieve threading dislocation density of (1.0 ± 0.3) × 107 cm−2 with a surface roughness of 10 nm RMS. No phase separation was observed during the InAlAs compositionally graded buffer layer growth. 1.4 μm long channel length transistors are fabricated from the wafer with IDS of 70 μA/μm and gm of above 60 μS/μm, demonstrating the high quality of the grown materials.