Automated sizing of low-noise CMOS analog amplifier using ALCPSO optimization algorithm

Abstract

The main aim of the automated design methodology is to improve the design process in terms of cost, robustness and performance. Presence of noise restricts the minimum level of signal that a circuit can processed with an acceptable quality which increases the complexity of the circuit. Optimization is a time consuming and difficult tasks that involves handling wide variety of conflicting constraints or design specifications and wide range of design parameters. In this paper, Particle Swarm Optimization with an Aging Leader and challengers (ALCPSO)-based design methodology is proposed. ALCPSO is used to search the solution space for computing the constraints and design parameters with main aim of simultaneously minimizing the thermal noise and area of the circuit. In other word, the proposed design methodology incorporate noise as design specification along with other specifications which were lacking in previous automated methodology. And this methodology gives a platform to optimize both length and width of MOS transistor which will further minimize the circuit area. The computation of the ALCPSO-design methodology is performed using MATLAB and is linked to CADENCE tool with 0.18 µm parameters technology to verify the ALCPSO-based design methodology.