Transistor Gate Length Research Articles

(Invited) High-Performance Field-Effect Transistors Based on Two-Dimensional Materials for VLSI Circuits

At present, silicon very large-scale integration has reached channel thicknesses of 7 nm. However, further scaling is becoming increasingly challenging as the gate electrostatics requires a significant reduction in channel thickness to about a fourth of the gate length. Consequently, the gate length of high-performance field-effect transistors is 16 nm at the state-of-the-art, and it is projected to stall at 12 nm for the 1.5 nm node and the following nodes, according to the International Roadmap for Devices and Systems. At these nodes, two-dimensional materials could potentially replace silicon as the channel material as they maintain sizable mobilities at atomic thicknesses, providing improved gate control in stacked channel nanosheet transistors. However,there are several challenges to overcome for FETs based on 2D mate-rials to serve as the front-end devices in VLSI circuits.

The insight and evaluation of ultra-scaled sub-1 nm gate length transistors

There is a great attention of scaling down transistor based on 2D materials. Although gate-all-around (GAA) structure based on silicon has been simulated, the GAA structure combined with 2D materials do not have a well understanding. Moreover, the recent proposed edge graphene gated transistor also needs deeper analysis. Here, edge graphene gated 2D-FETs are further investigated and optimized by employing semi-classical numerical method. The physical dimensions can be optimized to obtain performance improvement, and some possible schemes are proposed. We demonstrate fair quantitative comparison for our proposed 0.34 nm graphene edge gated MoS2 and GAA graphene gated silicon nanowire device structure. It is found that the edge graphene gated MoS2 FET can achieve superior short channel performance compared to GAA graphene gated silicon nanowire and traditional GAA silicon nanowire FET, due to the generic nature of 2D TMDs, which possess direct narrow bandgap, low dielectric constant and atomic thickness. We have figured out that the 0.34 nm edge graphene gated MoS2 FET has even better subthreshold swing than the Si-GAA and Graphene-GAA, which shows promising prospect as next generation electronics.

Metal Additive Microfabrication of System-in-Package with Embedded Microfluidic Thermal Management for Heterogeneous Integration with Semiconductor Dies

The scaling of components on a single semiconductor chip has enabled the doubling of performance every 2 years as per Moore’s law, and has been possible due to the miniaturization of individual components. A significant decrease in transistor gate length and increase in component density has also introduced an increase in power density. Hence, there is a dire need for embedded thermal management of these systems-on-chips (SoCs) to remove waste heat. In this work, the metal additive microfabrication of a system-in-package (SiP) package with multiple pads for quad flat no-lead (QFN) packaging and a microfluidic channel and pin fin heat sinks for thermal management are presented. This work introduces heterogeneous integration (integration of separately manufactured components into a SiP for improved functionality) of SiPs fabricated using additive microfabrication to clean-room-fabricated integrated circuits (ICs) for improved functionality in terms of the thermal management of high-power density SoCs. The packages have been fabricated via a metal additive manufacturing technique, direct metal laser sintering (DMLS), using 316L stainless steel as the precursor powder. The work also opens doors to the fabrication and integration of metal microsystems using DMLS to complement semiconductor manufacturing and packaging processes. The use of air or water as the coolant for the packaging devices decreased the thermal resistance from 5.25°C/W for the conventional packages to 2.02°C/W for a flow rate of 84 mL/min when subjected to a constant heat flux. The average surface temperature also decreased from 45.61°C to 29.23°C for the same parameter. This article details the material characteristics and thermal performance of the metal additively microfabricated SiPs.

Sub-9 nm high-performance and low-power transistors based on an in-plane NbSe2/MoSe2/NbSe2 heterojunction.

Due to the ability to reduce the gate length of field-effect transistors (FETs) down to sub-10 nm without obviously affecting the performance of the device, the utilization of two-dimensional (2D) semiconductor materials as channel materials for FETs is of great interest. However, in-plane 2D/2D heterojunction FETs have received less attention in previous studies than vertical van der Waals heterojunction devices. Based on the above reasons, this study has investigated the transport properties of an in-plane NbSe2/MoSe2/NbSe2 heterojunction FET with different gate lengths by using ab initio quantum transport simulation. The results reveal that a gate length of sub-9 nm gives the device a low subthreshold swing down to 62 mV dec-1 and a high on-state current up to 1040 μA μm-1. Most importantly, the on-state current, delay time, and power dissipation of the FET with the optimized channel length can nearly meet or even exceed the high-performance and low-power requirements of the International Technology Roadmap for Semiconductors. The findings for this FET can provide the design and development guidance for other in-plane heterojunction electrical devices in the post-Moore era.

Ka-Band High-Linearity and Low-Noise Gallium Nitride MMIC Amplifiers for Spaceborne Telecommunications

Gallium Nitride is becoming an interesting solution for low-noise applications in the lower part of the millimetre-wave spectrum and is gaining increasing attention in the space community for microwave receiver functionalities. Lately, its maturity level has increased and its performance in terms of noise figure and operating frequency is reaching other advanced III-V technologies such as Gallium Arsenide and Indium Phoshpide. Moreover, Gallium Nitride features higher power handling capability in comparison to the previously mentioned III-V technologies. In this context, we have designed and characterized two demonstrator circuits of critical microwave receiver functionalities: a Low-Noise Amplifier and a Low-Distortion Amplifier operating at Ka-band. It is shown that GaN circuits compare well in terms of noise figure, gain, and operating frequency with respect to other advanced III-V technologies, and most of all exhibit superior linearity in terms of intermodulation distortion. The designed Low-Noise Amplifier exhibits state-of-the-art 1.2 dB Noise Figure in the 27-31 GHz bandwidth thanks to a profitable combination of 60- and 100-nm gate length transistors on the same MMIC. On the other hand, the Low-Distortion Amplifier features state-of-the-art +30 dBm Output Third Order Intercept point in the same operating bandwidth while requiring only 216 mW dc power. The presented electrical performances are validated by comparing these designs to others available in open literature through figures of merit that normalize trade-offs by transistor length (therefore a fair comparison) aiming to highlight the merits of the proposed design methodologies.

Unveiling a geometric angstrom era of transistors: Physical gate length scaled down to one atom thickness

The world shortest gate length transistor was born using MoS2 as channel and the edge of graphene as gate, exhibiting on/off ratios up to 1.02 × 105 and subthreshold swing values down to 117mVdec−1. This work unveils that the geometric Angstrom era of transistors has come into reality. However, there is still a long way to go for the sub-1 nm- Lg transistors form the lab to the fab.

AlGaN/GaN High Electron Mobility Transistors Grown by MOVPE on 3C-SiC/Si(111) for RF Applications

In this work, an AlGaN/GaN HEMT structure is grown on a 0.8 μm thick 3C-SiC layer on high resistivity Silicon substrate. The RF propagation losses are investigated and compared with the ones of epi-layers grown directly on Silicon and on 6H-SiC substrates. Short gate length transistors are fabricated using e-beam lithography. In spite of ohmic contact resistance of 0.6 Ω.mm, a saturated current density of 0.7 A/mm at a gate bias of +1V and a transconductance peak higher to 250 mS/mm for 75 nm T-shaped gate transistors are reached on structure with thick 3C-SiC template. Moreover, for the first time, transition frequencies fT/fmax of 60/98 GHz are reported on such 3C-SiC template.

Can Carbon Nanotube Transistors Be Scaled Down to the Sub-5 nm Gate Length?

Single-walled carbon nanotubes (CNTs) have been considered as a promising semiconductor to construct transistors and integrated circuits in the future owing to their ultrathin channel thickness and ultrahigh injection velocity. Although a 5 nm gate-length CNT field-effect transistor (FET) has already been experimentally fabricated and demonstrates excellent device performance, the potential or constraint factors on performance have not been explored or revealed. Based on the benchmark of the device performance between the experimental and simulated 5 nm gate-length CNT FETs, we use the first-principles quantum transport approach to explore the performance limit of CNT FETs based on the gate-all-around (GAA) device geometry for the first time. It is found that the GAA CNT FETs can fulfill the ITRS 2028 high-performance target in the 2 nm gate-length node in terms of the on-state current, delay time, and power consumption. We also find that the energy-delay product of the CNT FETs is superior to those of the high-performance 2D materials and Si Fin FETs at the sub-5 nm gate length due to its unique electrical property. Though theoretically the gate length of CNT FETs can be potentially scaled to 2 nm, considering the tradeoff between the performance and power consumption, 5 nm is the ultimate scaled limit.

Millimeter-Wave Vertical III-V Nanowire MOSFET Device-to-Circuit Co-Design

Vertical III-V nanowire MOSFETs show potential towards the ultimate transistor scaling. A high transconductance and current density are achieved based on the gate-all-around architecture. This work presents a high-frequency design of such devices, achieving more than 600 GHz cut-off frequencies ( f T, f max), at 20 nm gate length. Furthermore, capacitance design and scaling trends, supported by COMSOL Multiphysics simulations derive state-of-the-art parasitics magnitudes for vertical devices in general, reaching gate-drain capacitance values of 17 aF/wire, corresponding to 0.2 fF/μm. A unique co-designed feedback resonant circuit makes the device unilateral, exhibiting up to 15 dB gain in D-band at 0.5 V supply, and with a current density of 0.5 mA/μm. Finally, a 2-stage low noise amplifier is designed using an optimum matching concept to utilize the full available bandwidth. The resulting circuit performance is independent of transistor gate length, since any decrease in device intrinsic capacitance is assisted by an increase in device overlap capacitances in a setting unique to a current implementation of vertical nanowire MOSFETs. With this approach, amplifiers are designed with more than 20 dB gain and minimum noise figure of 2.5 dB in a simulation environment at 140 GHz. The proposed technology and design platform show a great potential in future low-power communication systems.

Quantum Dot With a Diamond-Shaped Channel MOSFET on a Bulk Si Substrate

In this article, a p-type high- ${k}$ /metal gate (HKMG) FinFET with a special diamond-shaped channel on a bulk Si substrate for the formation of gate-induced quantum dot (QD) is reported. The electrical characteristics of the device at various temperatures and bias voltages for QD formation are extensively investigated. Remarkable oscillations in the drain current are observed for the 30-nm gate length ( ${L}_{g}$ ) transistor at ${T} =20$ K. By analyzing the experimental results as well as the simulation data obtained by TCAD, it is found that the carriers are strongly localized at the small sharp tip of the channel and the thick spacers contribute to a large confinement potential for forming QD with a large charging energy of 30 meV. This provides a promising approach for large-scale QD fabrication and integration using the mainstream bulk complementary metal oxide semiconductor (CMOS) process.

Effect of the Front and Back Illumination on Sub-Terahertz Detection Using n-Channel Strained-Silicon MODFETs

Plasma waves in semiconductor gated 2-D systems can be used to efficiently detect Terahertz (THz) electromagnetic radiation. This work reports on the response of a strained-Si Modulation-doped Field-Effect Transistor (MODFET) under front and back sub-THz illumination. The response of the MODFET has been characterized using a two-tones solid-state continuous wave source at 0.15 and 0.30 THz. The DC drain-to-source voltage of 500-nm gate length transistors transducing the sub-THz radiation (photovoltaic mode) exhibited a non-resonant response in agreement with literature results. Two configurations of the illumination were investigated: (i) front side illumination in which the transistor was shined on its top side, and (ii) back illumination side where the device received the sub-THz radiation on its bottom side, i.e., on the Si substrate. Under excitation at 0.15 THz clear evidence of the coupling of terahertz radiation by the bonding wires was found, this coupling leads to a stronger response under front illumination than under back illumination. When the radiation is shifted to 0.3 THz, as a result of a lesser efficient coupling of the EM radiation through the bonding wires, the response under front illumination was considerably weakened while it was strengthened under back illumination. Electromagnetic simulations explained this behavior as the magnitude of the induced electric field in the channel of the MODFET was considerably stronger under back illumination.

Indium-Tin-Oxide Transistors with One Nanometer Thick Channel and Ferroelectric Gating.

In this work, we demonstrate high-performance indium-tin-oxide (ITO) transistors with a channel thickness down to 1 nm and ferroelectric Hf0.5Zr0.5O2 as gate dielectric. An on-current of 0.243 A/mm is achieved on submicron gate-length ITO transistors with a channel thickness of 1 nm, while it increases to as high as 1.06 A/mm when the channel thickness increases to 2 nm. A raised source/drain structure with a thickness of 10 nm is employed, contributing to a low contact resistance of 0.15 Ω·mm and a low contact resistivity of 1.1 × 10-7 Ω·cm2. The ITO transistor with a recessed channel and ferroelectric gating demonstrates several advantages over 2D semiconductor transistors and other thin-film transistors, including large-area wafer-size nanometer thin-film formation, low contact resistance and contact resistivity, an atomic thin channel being immune to short channel effects, large gate modulation of high carrier density by ferroelectric gating, high-quality gate dielectric and passivation formation, and a large bandgap for the low-power back-end-of-line complementary metal-oxide-semiconductor application.

Overview of Bias Temperature Instability in Scaled DRAM Logic for Memory Transistors

Continued scaling of DRAM technologies has required a limitation of the power dissipation from the logic components on-chip, while downscaling both transistor oxide thickness and gate length. One route to enable further scaling, while circumventing excessive leakage currents, is the integration of high-permittivity ( ${\kappa }$ ) metal-gate (HKMG) components into the logic and high-voltage (e.g., I/O) devices. The requirement of a gate-first flow for devices in the peripheral region introduces significant reliability challenges. Even though Negative Bias Temperature Instability (NBTI) performance of CMOS and memory thermal budget compatible transistors are aligned with conventional HKMG integration with thin oxide devices, it is not the case for thick oxide devices. In particular, it will be shown that strong NBTI lifetime degradation is observed as soon as high- ${\kappa }$ layers are deposited on top of the thick interfacial layer. In this work, a review of the impact of these high- ${\kappa }$ layers on the NBTI high voltage logic for memory devices is presented. The stress induced degradation is correlated to a diffusion of metal atoms from the HKMG gate stack towards the silicon surface. Directions for reliability improvements are then defined. The presence of Nitrogen throughout the HKMG stack can originate either from high- ${\kappa }$ processing or metal-nitride gate electrode. It is shown that preventing nitrogen diffusion towards the Si/SiO2 interface region, together with AlOx and/or F incorporation at the HKMG interface, can tune device threshold voltage and modulate access to donor trap-defect bands. The result of these effects is a vast improvement in NBTI performance. A detailed study of NBTI-degradation, supported by physical analysis, assessing the impact of various tuning components within the stack (interface layer, high- $\kappa $ fluorination and/or cap, metal gate) will be presented. Potential solutions for this reliability challenge will be reported.

Modeling and Evaluating the Gate Length Dependence of BTI

Bias temperature instability (BTI) is a major reliability concern in the current and upcoming technologies. Current mitigation techniques mainly target circuit and system levels through reducing the stimuli that govern BTI. Such mitigation techniques typically come with non-negligible overheads, which might not be acceptable—especially in smaller technology nodes where the available design margins are tighter. Semiconductor vendors report different BTI degradations in their technology and hence circuit designers need to consider such technology features when designing for reliability. Recently, TSMC reported that BTI strongly depends on the gate length ( ${L}$ ) of transistors in their 10nm technology node. In this brief, we are the first to investigate the role that gate length dependence of BTI may play as a new degree of freedom in the design for reliability. Based on the reported data from TSMC, we propose to incorporate the gate length dependency into a state-of-the-art physics-based BTI model. Then, we propose a new method of transistor stacking that optimizes circuits (e.g., SRAM cells) with respect to on/off current ratios in which ${L}$ -dependency of BTI is taken into account. Compared to state of the art, our approach results in BTI-hardened SRAM cells with 50% better on/off current ratio along with $3\times$ better reliability at the cost of a 20% area overhead.

Insight Into Ballisticity of Room-Temperature Carrier Transport in Carbon Nanotube Field-Effect Transistors

Carbon nanotube field-effect transistors (CNT FETs) with gate length down to 10 nm are fabricated and analyzed by fitting the experimental data through the virtual-source (VS) model. Due to the quasi-ballistic carrier transport property, it is shown that carriers in CNTs exhibit the injection velocity of ${3}\times 10^{{7}}$ cm/s, approximately two times of the target velocity in the 10-nm gate length transistors required by International Roadmap for Devices and Systems (IRDS 2017). The transport parameters for the first time, namely, critical length, unidirectional thermal velocity, and backscattering mean free path (MFP), are extracted by the Lundstrom model from the measured data of quasi-ballistic short-channel CNT FETs to diffusive long-channel CNT FETs, which help arriving at a conclusion that, down to 10-nm gate length, the CNT FETs operate close to 73% of the ballistic regime.

Excess OFF-State Current in InGaAs FinFETs: Physics of the Parasitic Bipolar Effect

InGaAs FinFETs are challenged by relatively high leakage current in the OFF state. This originates from band-to-band tunneling (BTBT) at the drain end of the channel that is amplified by a parasitic bipolar effect (PBE) as a result of its floating body. In this paper, we present a simple model of the PBE in InGaAs FinFETs, which captures the key gate length and fin width dependences. Our model accounts for surface recombination at the sidewalls of the fin as well as bulk recombination at the heavily doped source. When compared with experimental results, our model suggests that fin sidewall recombination dominates in long gate length transistors and leads to an exponential gate length dependence of the current gain on the parasitic bipolar junction transistor (BJT). The model enables the extraction of the carrier diffusion length which exhibits the predicted fin width dependence. For short gate length transistors, source recombination is shown to dominate and the parasitic bipolar gain scales with the inverse of the gate length.

Polarization Engineering of AlGaN/GaN HEMT With Graded InGaN Sub-Channel for High-Linearity X-Band Applications

We report on the power and linearity performance of metal-organic chemical vapor deposition grown polarization-engineered novel structure that combines the AlGaN/GaN high-electron-mobility transistor with a graded InGaN sub-channel layer. The fabricated transistors with composite two-dimensional(2D) and three-dimensional(3D) electron channels showed nearly flat transconductance and power gain profiles. The maximum f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> and f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> values of 18 GHz and 38 GHz were measured for 0.7-μm gate-length transistors. Load-pull measurement at 10 GHz revealed a maximum output power of 2.2 W/mm. Two-tone measurement at 10 GHz showed an excellent OIP3 of 38 dBm for 150-μm device width and a corresponding linearity figure of merit OIP3/P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DC</sub> of 9.7 dB. These results suggest that InGaN-based composite 2D-3D channel transistors could be useful for high-frequency applications requiring high linearity.

X-Band Power and Linearity Performance of Compositionally Graded AlGaN Channel Transistors

We report on the power and linearity performance of metal organic chemical vapor deposition grown AlGaN channel polarization-graded field-effect transistor (PolFET). The fabricated transistors with 3-D electron channels showed nearly flat transconductanceprofiles. Maximum f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> and fmax of 23 and 65 GHz were measured for 0.7-μm gate-length transistors, corresponding to an f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> -L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> product of 16.2 GHz·μm. Load-pull measurement at 10 GHz revealed a maximum output power of 2 W/mm with a maximum small signal gain of 16 dB. Two-tone measurement at 10 GHz showed an OIP3 of 33 dBm for 150-μm device width and a corresponding linearity figure-of-merit OIP3/PDC of 3.4 dB. These results suggest that PolFETs could be useful for high-frequency applications requiring high linearity.

Physical insights into the operation of a 1-nm gate length transistor based on MoS2 with metallic carbon nanotube gate

Low-dimensional materials such as layered semiconductors or carbon nanotubes (CNTs) have been attracting increasing attention in the last few decades due to their inherent scaling properties, which become fundamental to sustain the scaling in electronic devices. Inspired by recent experimental results [Desai et al., Science 354, 99 (2016)], in this work we examined the ultimate performance of MoS2-channel Field Effect Transistors with a gate length of 1 nm by means of quantum transport simulations based on the Poisson equation and non-equilibrium Green's function formalism. We considered uniformly scaled devices, with channel lengths ranging from 5 to 20 nm controlled by a cylindrical gate with a diameter of 1 nm, as would be required in realistic integrated circuits. Moreover, we also evaluated the effect of the finite density of states of a carbon nanotube gate on the loss of device performance. We noticed that the sub-threshold swing for all short-channel structures was greater than the ideal 60 mV per decade limit of thermionic devices, and we attributed this to the presence of tunneling currents and gate-drain interactions. We tailored the transistor architecture in order to improve the gate control. We concluded that the limited CNT-channel capacitive coupling poses severe limitations on the operation and thus exploitation of the device.

Towards understanding recovery of hot-carrier induced degradation

This article treats the recovery of hot-carrier degraded nMOSFETs by annealing in a nitrogen ambient. The recovery rate is investigated as a function of the annealing temperature, where the recovery for increasing temperatures is in agreement with the passivation processes. At the original post-metal anneal temperature of T = 400 °C, the device's original performance is fully restored. Higher temperatures induce a permanent, unrecoverable change to the devices, manifested in a gradual VT shift. The recovery rate is found to be independent of both the transistor gate length and the cooling rate (quench, slow and stepped cooling) upon annealing. These findings are used to gain further understanding of the mechanisms behind the recovery of hot-carrier damage. The recovery rate exhibits Arrhenius behavior and the recovery data are consistent with Stesmans' recovery model.