Transistor Gate Length Research Articles

NEGF simulations of the effect of strain on scaled double gate nanoMOSFETs

The effect of biaxial strain on double gate (DG) nanoscaled Si MOSFET with channel lengths in the nanometre range is investigated using Non-Equilibrium Green’s Functions (NEGF) simulations. We have employed fully 2D NEGF simulations in order to answer the question at which body thickness the effects of strain is masked by the confinement impact. Following ITRS, we start with a 14 nm gate length DG MOSFET having a body thickness of 9 nm scaling the transistors to gate lengths of 10, 6 and 4 nm and body thicknesses of 6.1, 2.6 and 1.3 nm. The simulated ID–VG characteristics show a 6% improvement in the on-current for the 14 nm gate length transistor mainly due to the energy separation of the Δ valleys. The strain effect separates the 2 fold from the 4 fold valleys thus keeping mostly operational transverse electron effective mass in the transport direction. However, in the device with an extreme body thickness of 1.3 nm, the strain effect has no more impact on the DG performance because the strong confinement itself produces a large energy separation of valleys.

Impact of strain on scaling of Double Gate nanoMOSFETs using NEGF approach

AbstractThe effect of biaxial strain on double gate (DG) nanoscaled MOSFET with channel lengths in the nanometre range is investigated using Non‐Equilibrium Green's Functions (NEGF) simulations. The NEGF simulations are fully 2D in order to accurately evaluate the effects of strain in strongly confined channels. Starting with a 14 nm gate length DG MOSFET with a corresponding body thickness of 9 nm we scale the transistors to gate lengths of 10, 6 and 4 nm and body thicknesses of 6.1, 2.6 and 1.3 nm, respectively. The simulated ID‐VG characteristics show 11% improvement in the oncurrent for the 14 nm gate length transistor due to the Δ valley splitting. This improvement in the on‐current is due to separate contributions from the 2 fold and 4 fold valleys to the carrier transport. However, in the device with an extreme body thickness of 1.3 nm the strain has no impact on its performance because the strong confinement itself produces a large valley splitting. (© 2008 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Low electron mobility of field-effect transistor determined by modulated magnetoresistance

Room temperature magnetotransport experiments were carried out on field-effect transistors in magnetic fields up to 10 T. It is shown that measurements of the transistor magnetoresistance and its first derivative with respect to the gate voltage allow the derivation of the electron mobility in the gated part of the transistor channel, while the access/contact resistances and the transistor gate length need not be known. We demonstrate the potential of this method using GaN and Si field-effect transistors and discuss its importance for mobility measurements in transistors with nanometer gate length.

Sub-30-nm hybrid lithography (electron beam∕deep ultraviolet) and etch process for fully depleted metal oxide semiconductor transistors

Fully depleted silicon on insulator (FDSOI) devices with high-k dielectrics and metal gate are promising candidates for sub-45-nm complementary metal oxide semiconductor technologies. At present, the gate length reduction becomes more and more difficult due to resist thickness diminution induced by critical dimension downscaling. In order to suppress resist thickness limitations, we have added a carbon layer with a SiO2 capping onto the conventional dielectric hard mask (SiO2 or Si3N4). In this study, FDSOI transistors with hafnium dielectric (HfO2), titanium nitride (TiN) metal gate were patterned by combining high resolution hybrid lithography (electron beam∕deep ultraviolet) and amorphous carbon hard mask. Full three-dimensional (3D) characterizations were carried out by using 3D atomic force microscope (CD-AFM from Veeco) to determine the best process window. Finally, after carbon hard mask trimming, sub-30-nm gate length transistors were achieved and successfully electrically tested.

SEMICONDUCTOR DEVICE SCALING: PHYSICS, TRANSPORT, AND THE ROLE OF NANOWIRES

Nanoelectronics (including nanomagnetics and nanophotonics) generally refers to nanometer scale devices, and to circuits and architectures which are composed of these devices. Continued scaling of the devices into the nanometer range leads to enhanced information processing systems. Generally, this scaling has arisen from three major sources, one of which is reduction of the physical gate length of individual transistors. Until recently, this has also allowed an increase in the clock speed of the chip, but power considerations have halted this to levels around 4 GHz in Si. Indeed, there are indications that scaling itself may be finished by the end of this decade. Instead, there are now pushes to seek alternative materials for nano-devices that may supplement the Si CMOS in a manner that allows both higher speeds and lower power. In this paper, we will cover some of the impending limitations, and discuss some alternative approaches that may signal continued evolution of integrated circuits beyond the end of the decade.

Noise Optimization of Charge Amplifiers With MOS Input Transistors Operating in Moderate Inversion Region for Short Peaking Times

The noise of a fast charge sensitive amplifier (CSA) with an input MOS transistor operating in the moderate inversion region is discussed. The MOS transistor operation in the moderate inversion region becomes especially important in multichannel readout systems where limited power dissipation is required. The ENC of a CSA followed by a fast shaper is usually dominated by the voltage noise of the input MOS transistor. We carried out noise minimization for such a CSA, searching for an optimum input transistor width. The analyses were made using a simplified EKV model and were compared to HSPICE simulations using a BSIM3v3 model. We considered several CMOS technology generations with minimum transistor gate length ranging from 0.13 mum to 0.8 mum. We studied the sensitivity of ENC to the input transistor width, and propose a simple formula to estimate the optimum transistor width, which is valid in a wide current density range.

Reduced Parameter Fluctuation with Laser and Flash Lamp Anneal for 65nm Volume Production

Process parameter fluctuations have a strong impact on functionality and performance of CMOS logic circuits and memory cells. Tight control of transistor gate length and final anneal temperature are equally important. We have developed a strategy to monitor these fluctuations which takes into account the full complexity of advanced microprocessors with large cache cell areas. This paper shows that reducing the anneal temperature reduces the parameter fluctuations. Transistor performance degradation at reduced temperatures can be compensated by using advanced annealing techniques like Laser or Flash lamp anneal. These techniques do not result in additional parameter fluctuation.

Monte Carlo Simulations of High-Performance Implant Free In$_{0.3}$Ga$_{0.7}$As Nano-MOSFETs for Low-Power CMOS Applications

The potential performance of implant free heterostructure In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.3</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.7</sub> As channel MOSFETs with gate lengths of 30, 20, and 15 nm is investigated using state-of-the-art Monte Carlo (MC) device simulations. The simulations are carefully calibrated against the electron mobility and sheet density measured on fabricated III-V MOSFET structures with a high-kappa dielectric. The MC simulations show that the 30 nm gate length implant free MOSFET can deliver a drive current of 2174 muA/mum at 0.7 V supply voltage. The drive current increases to 2542 muA/mum in the 20 nm gate length device, saturating at 2535 muA/mum in the 15 nm gate length one. When quantum confinement corrections are included into MC simulations, they have a negligible effect on the drive current in the 30 and 20 nm gate length transistors but lower the 15 nm gate length device drive current at 0.7 V supply voltage by 10%. When compared to equivalent Si based MOSFETs, the implant free heterostructure MOSFETs can deliver a very high performance at low supply voltage, making them suitable for low-power high-performance CMOS applications

Speeding up VLSI Layout Verification Using Fuzzy Attributed Graphs Approach

Technical and economic factors have caused the field of physical design automation to receive increasing attention and commercialization. The steady down-scaling of complementary metal oxide semiconductor (CMOS) device dimensions has been the main stimulus to the growth of microelectronics and computer-aided very large scale integration (VLSI) design. The more an Integrated Circuit (IC) is scaled, the higher its packing density becomes. For example, in 2006 Intel's 65-nm process technology for high performance microprocessor has a reduced gate length of 35 nanometers. In their 70-Mbit SRAM chip, there are up to 0.5 billion transistors in a 110 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> chip size with 3.4 GHz clock speed. New technology generations come out every two years and provide an approximate 0.7 times transistor size reduction as predicted by Moore's Law. For the ultimate scaled MOSFET beyond 2015 or so, the transistor gate length is projected to be 10 nm and below. The continually increasing size of chips, measured in either area or number of transistors, and the wasted investment involving fabricating and testing faulty circuits, make layout analysis an important part of physical design automation. Layout-versus-schematic (LVS) is one of three kinds of layout analysis tools. Subcircuit extraction is the key problem to be solved in LVS. In LVS, two factors are important. One is run time, the other is identification correctness. This has created a need for computational intelligence. Fuzzy attributed graph is not only widely used in the fields of image understanding and pattern recognition, it is also useful to the fuzzy graph matching problem. Since the subcircuit extraction problem is a special case of a general-interest problem known as subgraph isomorphism, fuzzy attributed graphs are first effectively applied to the subgraph isomorphism problem. Then we provide an efficient fuzzy attributed graph algorithm based on the solution to subgraph isomorphism for the subcircuit extraction problem. Similarity measurement makes a significant contribution to evaluate the equivalence of two circuit graphs. To evaluate its performance, we compare fuzzy attributed graph approach with the commercial software called SubGemini, and two of the fastest approaches called DECIDE and SubHDP. We are able to achieve up to 12 times faster performance than alternatives, without loss of accuracy

Low temperature electron mobility and concentration under the gate of AlGaN∕GaN field effect transistors

High electron mobility field effect transistors were fabricated on AlGaN∕GaN heterostructures and their magnetoresistance was measured at 4.2K up to 10T with simultaneous modulation of the gate potential. Low and high magnetic field data were used to determine the electron mobility (μ) and concentration (n), respectively, in the gated part of the transistor channel. With these measurements we present a method to determine μ and n under the gate of a transistor, which does not require knowledge of the transistor gate length, access resistance, threshold voltage, or capacitance. We discuss applications of this method for nanometer and ballistic transistors.

Application of Aberration-Corrected TEM and Image Simulation to Nanoelectronics and Nanotechnology

The image quality in electron microscopy often suffers from lens aberration. As a result of lens aberrations, critical information appears distorted at the atomic scale in high-resolution transmission electron microscopy (HRTEM). In scanning TEM (STEM), the spatial resolution of images and the quality of spectroscopic data are greatly reduced. With the recent introduction of aberration-corrected lenses and monochromators, new and exciting images with sub-0.1-nm spatial resolution are now recorded routinely, and electron energy loss data has been used to determine the location of a single atom in an atomic column. As a result of the decreased focal depth of an aberration-corrected lens used in STEM, the dream of three-dimensional (3-D) atomic resolution is one step closer and for HRTEM it was shown that 3-D imaging with atomic resolution is feasible. However, understanding imaging and spectroscopy in HRTEM and STEM still requires refined modeling of the underlying electron scattering processes by multislice image simulation. Since research into the physics and technology of nanoelectronic devices has already moved into sub-10-nm transistor gate lengths, the need for well-understood imaging and spectroscopy at nanoscale dimensions is already upon us. Fortunately, nanowires and other nanotechnology materials serve as useful test samples as well as being potential materials for future nanoelectronics. This enables early development of microscopy methods that will be used to investigate future generations of integrated circuits

Design of low noise charge amplifier in sub-micron technology for fast shaping time

A discussion of the noise optimisation of the fast charge sensitive amplifier (CSA) for imaging systems using highly segmented semiconductor detectors is presented. In such systems a limited power dissipation per single channel is available while a good noise performance and a fast signal processing time are required. This paper describes the CSA noise optimisation for several CMOS technology generations with the minimum transistor gate length ranging from 0.13?m to 0.8?m and for a detector capacitance in the range from 0.5 pF to 12 pF. In a well-designed CSA, followed by a fast shaper stage, an equivalent noise charge (ENC) is dominated by the thermal noise of an input MOS transistor. In the applications considered the input transistor usually works in a moderate inversion region where no simple formula for the noise performance exists. Our analyses are made using a simplified EKV model and are compared with HSPICE simulations using BSIM3v3 models. We show several novel aspects of the noise optimisation of the CSA regarding the optimum transistor width and the sensitivity of the ENC to this width.

Heat Generation and Transport in Nanometer-Scale Transistors

As transistor gate lengths are scaled towards the 10-nm range, thermal device design is becoming an important part of microprocessor engineering. Decreasing dimensions lead to nanometer-scale hot spots in the transistor drain region, which may increase the drain series and source injection electrical resistances. Such trends are accelerated by the introduction of novel materials and nontraditional transistor geometries, including ultrathin body, FinFET, or nanowire devices, which impede heat conduction. Thermal analysis is complicated by subcontinuum phenomena including ballistic electron transport, which reshapes the heat generation region compared with classical diffusion theory predictions. Ballistic phonon transport from the hot spot and between material boundaries impedes conduction cooling. The increased surface to volume ratio of novel transistor designs also leads to a larger contribution from material boundary thermal resistance. This paper surveys trends in transistor geometries and materials, from bulk silicon to carbon nanotubes, along with their implications for the thermal design of electronic systems

Non Resonant Response to Terahertz Radiation by Submicron CMOS Transistors

Experimental investigations on detection of terahertz radiation are presented. We used plasma wave instability phenomenon in nanometer Silicon field effect transistor. A 30 nm gate length transistor was illuminated by THz radiation at room temperature. We observe a maximum signal near to the threshold voltage. This result clearly demonstrates the possibility of plasma wave THz operation of these nanometer scale devices. The response was attributed to a non resonant detection. We also demonstrate the possibility to observe a resonant detection on the same devices.

Analytical modeling of CMOS circuit delay distribution due to concurrent variations in multiple processes

A technique for modeling the effect of variations in multiple process parameters on circuit delay performance is proposed. The variation in saturation current Ion at the device level, and the variation in rising/falling edge stage delay for the NAND gate at the circuit level, are taken as performance metrics. The delay of a two-input NAND gate with 65nm gate length transistors is extensively characterized by mixed-mode simulations, which is then used as a library element. Appropriate templates for the NAND gate library are incorporated in a general purpose circuit simulator SEQUEL. A 4-bit×4-bit Wallace tree multiplier circuit, consisting of two-input NAND gates is used to demonstrate the proposed methodology. The variation in the multiplier delay is characterized, by generating delay distributions, using an extensive Monte Carlo analysis. The use of linear interpolation and linear superposition is evaluated to study simultaneous variations in two and more process parameters. An analytical model for gate delays, in terms of device drive current Ion, is proposed, which can be used to extend this methodology for a generic technology library with a variety of library elements. The model is validated against Monte Carlo simulations and is shown to have a typical error of less than 0.1% for simultaneous variations in multiple process parameters. The proposed methodology can be used for statistical timing analysis and circuit simulation at the gate level.

Thermal Phenomena in Nanoscale Transistors

As CMOS transistor gate lengths are scaled below 45nm, thermal device design is becoming an important part of microprocessor engineering. Decreasing dimensions lead to nanometer-scale hot spots in the drain region of the device, which may increase the drain series and source injection electrical resistances. Such trends are accelerated with the introduction of novel materials and nontraditional transistor geometries, like ultrathin body, surround-gate, or nanowire devices, which impede heat conduction. Thermal analysis is complicated by subcontinuum phenomenan including ballistic electron transport, which reshapes the hot spot region compared with classical diffusion theory predictions. Ballistic phonon transport from the hot spot and between material boundaries impedes conduction cooling. The increased surface to volume ratio of novel transistor designs also leads to a larger contribution from material boundary thermal resistance. In this paper we survey trends in transistor geometries and materials, from bulk silicon to carbon nanotubes, along with their implications for the thermal design of electronic systems.

Effect of gate-drain/source overlap on the noise in 90nm N-channel metal oxide semiconductor field effect transistors

In this paper, we have studied the effect of gate-drain/source overlap (LOV) on the drain channel noise and induced gate current noise (SIg) in 90nm N-channel metal oxide semiconductor field effect transistors using process and device simulations. As the change in overlap affects the gate tunneling leakage current, its effect on shot noise component of SIg has been taken into consideration. It has been shown that “control over LOV” allows us to get better noise performance from the device, i.e., it allows us to reduce noise figure, for a given leakage current constraint. LOV in the range of 0–10nm is recommended for the 90nm gate length transistors, in order to get the best performance in radio frequency applications.

Monte-Carlo simulations of ion track in silicon and influence of its spatial distribution on single event effects

High energy interaction of heavy ions with silicon integrated circuits contribute to transient events or single event effects (SEE) when ionizing the device along the particle path. Knowledge of the electron–hole pair density in the ion track is necessary for studying collected charge and estimating device reliability for deep sub-micron transistors. We have simulated ion-tracks in silicon with a Monte-Carlo code, TRAMOS, which is reported in this paper. High velocity heavy ion interactions with silicon are described within the plane wave Born approximation. For electrons, differential cross-sections are calculated using the phase shift method for elastic collisions and the BEB model for inelastic interactions. Calculations show that for high ion velocities, a non-negligible fraction of the energy is deposited outside the sensitive volume of sub-micron transistors when compared to the case of the low ion velocities. The response of a silicon on insulator transistor to different ion tracks (size, density) is investigated with device simulations. Results show that for the 0.25 μm gate length transistor simulated, due to the technology used, the size of the ion track has minor effect on the collected charge Q c. For ions with same stopping power and different velocities, differences on Q c may show up, due to recombination mechanisms.

Quantitative analysis of ultrashallow junction of sub-50nm gate-length transistors: Junction depth, sheet resistance, short channel effects, and transistor performance

We analyzed causes of dopant loss in ultrashallow junction during complementary metal-oxide-semiconductor (CMOS) fabrication: (1) sputtering-out during ion implantation, (2) wet-etching removal in cleaning process, (3) outdiffusion, and (4) deactivation in post-thermal process. By using low energy electron induced x-ray emission spectrometry and other conventional analytic techniques such as four-point probe (FPP) and SIMS, the dopant losses are quantified. We developed a simple source/drain extension (SDE) sheet-resistance test structure to measure the actual sheet resistance of SDE to avoid sizable error due to FPP probe penetration. By comparing with CMOS electrical data, practical aspect of junction depth and sheet resistance is discussed in terms of short channel effects and on-state current. It is found that deactivation and wet-etching removal of arsenic dopant during cleaning process are the major factors in scaling of n-type transistor, while junction depth is the major one in scaling of p-type transistor.

Improvements in Polysilicon Etch Bias and Transistor Gate Control With Module Level APC Methodologies

The targeting of transistor gate length is a primary driver of device performance. The targeting of the physical gate critical dimension (CD) greatly impacts the electrical gate dimension. Traditionally, continual monitoring and manual offsets to compensate for lithographic and etch equipment variability have been used to control gate CDs. This paper discusses how advanced process control techniques were applied to the 0.13-/spl mu/m polysilicon (poly) patterning process. Both scanner and etch equipment were controlled using a combination of feedforward and feedback loops. As a result, significant engineering labor was saved, and gate CD 3 sigma results improved 12%, correlating to improved device performance and enhanced yield.