Transfer Gate Research Articles

Dependence of the Spill Back Effect on the Energy Level Distribution of Interface States Under the Transfer Gate in CMOS Image Sensor

Dependence of the Spill Back Effect on the Energy Level Distribution of Interface States Under the Transfer Gate in CMOS Image Sensor

The Effect of Pixel Design and Operation Conditions on Linear Output Range of 4T CMOS Image Sensors.

We analyze several factors that affect the linear output range of CMOS image sensors, including charge transfer time, reset transistor supply voltage, the capacitance of integration capacitor, the n-well doping of the pinned photodiode (PPD) and the output buffer. The test chips are fabricated with 0.18 μm CMOS image sensor (CIS) process and comprise six channels. Channels B1 and B2 are 10 μm pixels and channels B3-B6 are 20 μm pixels, with corresponding pixel arrays of 1 × 2560 and 1 × 1280 respectively. The floating diffusion (FD) capacitance varies from 10 fF to 23.3 fF, and two different designs were employed for the n-well doping in PPD. The experimental results indicate that optimizing the FD capacitance and PPD design can enhance the linear output range by 37% and 32%, respectively. For larger pixel sizes, extending the transfer gate (TG) sampling time leads to an increase of over 60% in the linear output range. Furthermore, optimizing the design of the output buffer can alleviate restrictions on the linear output range. The lower reset voltage for noise reduction does not exhibit a significant impact on the linear output range. Furthermore, these methods can enhance the linear output range without significantly amplifying the readout noise. These findings indicate that the linear output range of pixels is not only influenced by pixel design but also by operational conditions. Finally, we conducted a detailed analysis of the impact of PPD n-well doping concentration and TG sampling time on the linear output range. This provides designers with a clear understanding of how nonlinearity is introduced into pixels, offering valuable insight in the design of highly linear pixels.

A 4H-SiC p-channel insulated gate bipolar transistor with higher breakdown voltage and superior V F·C res figure of merit

A silicon carbide p-channel insulated gate bipolar transistor (IGBT) with higher breakdown voltage (BV) and low V F·C res figure of merit (FOM) has been simulated, fabricated, and characterized successfully. The proposed IGBT adds two n-type implant regions in the junction FET (JFET) area and increases the gate oxide thickness above the JFET area to reduce the reverse transfer capacitance (C res) and gate oxide electric field (E ox). The proposed structure notably lowers E ox below 3 MV cm−1 while elevating the BV to 16.6 kV. A new FOM of V F·C res is defined to evaluate the trade-off between the on-state and the C res characteristics. The experimental results demonstrate that a lower V F·C res FOM of 0.369 V·pF is achieved from the proposed IGBT with a reduction of 66.4%, compared to the conventional current spreading layer IGBT. Meanwhile, the simulated turn-on and turn-off times of the proposed IGBT are reduced by 29.4% and 20%, respectively.

Incomplete charge transfer in CMOS image sensor caused by Si/SiO2 interface states in the TG channel

CMOS image sensors produced by the existing CMOS manufacturing process usually have difficulty achieving complete charge transfer owing to the introduction of potential barriers or Si/SiO2 interface state traps in the charge transfer path, which reduces the charge transfer efficiency and image quality. Until now, scholars have only considered mechanisms that limit charge transfer from the perspectives of potential barriers and spill back effect under high illumination condition. However, the existing models have thus far ignored the charge transfer limitation due to Si/SiO2 interface state traps in the transfer gate channel, particularly under low illumination. Therefore, this paper proposes, for the first time, an analytical model for quantifying the incomplete charge transfer caused by Si/SiO2 interface state traps in the transfer gate channel under low illumination. This model can predict the variation rules of the number of untransferred charges and charge transfer efficiency when the trap energy level follows Gaussian distribution, exponential distribution and measured distribution. The model was verified with technology computer-aided design simulations, and the results showed that the simulation results exhibit the consistency with the proposed model.

Analysis of Light Intensity and Charge Holding Time Dependence of Pinned Photodiode Full Well Capacity.

In this paper, the light intensity and charge holding time dependence of pinned photodiode (PD) full well capacity (FWC) are studied for our pixel structure with a buried overflow path under the transfer gate. The formulae for PDFWC derived from a simple analytical model show that the relation between light intensity and PDFWC is logarithmic because PDFWC is determined by the balance between the photo-generated current and overflow current under the bright condition. Furthermore, with using pulsed light before a charge holding operation in PD, the accumulated charges in PD decrease with the holding time due to the overflow current, and finally, it reaches equilibrium PDFWC. The analytical model has been successfully validated by the technology computer-aided design (TCAD) device simulation and actual device measurement.

Sequential and Graphical Cross-Domain Recommendations with a Multi-View Hierarchical Transfer Gate

Cross-domain recommender systems could potentially improve the recommendation performance by means of transferring abundant knowledge from the auxiliary domain to the target domain. They could help address some key challenges in recommender systems, such as data sparsity and cold start. However, most existing cross-domain recommendation approaches represent the user preferences based on a single kind of user’s feature or behavior and fail to explore the hidden interaction effects of different kinds of features or behaviors. In this article, we propose the S equential and G raphical Cross -Domain Recommendations with a Multi-View Hierarchical Transfer Gate (SGCross) to transfer user representations from multiple perspectives. The SGCross model constructs a user profile by learning the personal preference from a personal view, the dynamic preference from a temporal view, as well as the collaborative preference from a collaborative view. Specifically, a Multi-view Hierarchical Gate (MHG) is designed to transfer the informative representations of user knowledge on different views from the auxiliary domain separately, aiming to enhance the user representations. Furthermore, a two-stage attentive fusion module is designed to integrate transferred information at two levels: the domain level and the view level. Extensive experiments on the Amazon dataset and the Douban dataset have demonstrated that SGCross effectively improves the accuracy of cross-domain recommendations and outperforms the state-of-the-art baseline models.

Design and Characterization of a Burst Mode 20 Mfps Low Noise CMOS Image Sensor.

This paper presents a novel ultra-high speed, high conversion-gain, low noise CMOS image sensor (CIS) based on charge-sweep transfer gates implemented in a standard 180 nm CIS process. Through the optimization of the photodiode geometry and the utilization of charge-sweep transfer gates, the proposed pixels achieve a charge transfer time of less than 10 ns without requiring any process modifications. Moreover, the gate structure significantly reduces the floating diffusion capacitance, resulting in an increased conversion gain of 183 µV/e-. This advancement enables the image sensor to achieve the lowest reported noise of 5.1 e- rms. To demonstrate the effectiveness of both optimizations, a proof-of-concept CMOS image sensor is designed, taped-out and characterized.

A Simulation Study of Junctionless Forksheet on Sub-2 nm Node Logic Applications

This article presents an evaluation of the CMOS logic performance of a junctionless (JL) forksheet based on 3-D numerical simulation. The study investigates the transfer characteristics and gate capacitance of the JL-forksheet with channel doping ranging from <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{1}\ttimes\text{10}^{\text{19}}$</tex-math> </inline-formula> to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{6}\ttimes\text{10}^{\text{19}}/\text{cm}^{\text{3}}$</tex-math> </inline-formula> , to determine the optimal performance of the device. Results show that due to its lower gate capacitance, the JL-forksheet has a lower intrinsic delay than the IM-forksheet. Moreover, the JL-forksheet demonstrates improved logic performance in terms of rise time, fall time, propagation delay, and maximum oscillation frequency, with improvements of at least 25%, 35%, 17%, and 21%, respectively, as compared to the IM-forksheet. Based on its simple fabrication process, better power efficiency, and improved digital logic performance at the sub-2 nm technology node (N2), the JL-forksheet exhibits strong potential as a high-performance CMOS logic solution in the post-Moore era.

Dark current in pinned photodiode CMOS image sensors: a pre-fabrication physics-based model

The present technique to find a dark current source in an image sensor, i.e., Dark Current Spectroscopy, is not sufficient to conclusively differentiate between the contribution of interface and bulk defect generation in a pixel. Also, the dark current data is available only post-fabrication. In this work, the Dark current versus Transfer Gate-off voltage curve is used to extract the defect density-cross-section product, activation energy and maximum carrier lifetime for two important device generation sites, i.e., interface under the Transfer Gate and Pinned Photodiode depletion region. A comprehensive analytical dark current model is formulated and validated using TCAD simulation and experimental data reported in the literature. The temperature variation is incorporated using the Arrhenius relation corresponding to the specific activation energy level. The proposed model along with the Arrhenius relation provides a sufficient pre-fabrication dark current estimate.

State Manipulation via the All‐Microwave Protocol in the Superconducting Qutrits

The quantum gate is the foundation of quantum computation and simulation in superconducting circuits. In recent years, quantum systems with three energy levels have attracted much attention. Therefore, it is essential to study the protocol of the quantum‐state transfer in qutrits. Herein, the all‐microwave schemes are studied to realize the state transfer and quantum gates. First, the ∣fg&gt;–∣ge&gt; transition is designed in a superconducting circuit with a relatively large coupling. We measured the Stark shift in cases where the experimental parameters did not satisfy the dispersive condition. Then, by carefully calibrating the pulse parameters, the regular Rabi oscillation and the state transfer are realized between the second excited state of two qubits via stimulated Raman adiabatic passage.

Fast and Robust Geometric Two-Qubit Gates for Superconducting Qubits and beyond

Quantum protocols based on adiabatic evolution are remarkably robust against imperfections of control pulses and system uncertainties. While adiabatic protocols have been successfully implemented for quantum operations such as quantum state transfer and single-qubit gates, their use for geometric two-qubit gates remains a challenge. In this paper, we propose a general scheme to realize robust geometric two-qubit gates in multilevel qubit systems where the interaction between the qubits is mediated by an auxiliary system (such as a bus or coupler). While our scheme utilizes stimulated Raman adiabatic passage (STIRAP), it is substantially simpler than STIRAP-based gates that have been proposed for atomic platforms, requiring fewer control tones and ancillary states, as well as utilizing only a generic dispersive interaction. We also show how our gate can be accelerated using a shortcuts-to-adiabaticity approach, allowing one to achieve a gate that is both fast and relatively robust. We present a comprehensive theoretical analysis of the performance of our two-qubit gate in parametrically modulated superconducting circuits comprising two fluxonium qubits coupled to an auxiliary system.

Simulation and design of a burst mode 20Mfps global shutter high conversion gain CMOS image sensor in a standard 180nm CMOS image sensor process using sequential transfer gates

A sequential transfer-gate and photodiode optimization method for CMOS Image sensors are described in this paper, which enables the design of large-scale ultra-high-speed burst mode CMOS Image sensors in a low-cost standard CMOS Image sensor process without the need for process customization or advanced process. The sequential transfer gates also show a clear advantage in minimizing the floating diffusion capacitance and improving image sensor conversion gain in large-scale pixels.

Influence of Pixel Design on Charge Transfer in Pinned Photodiode CMOS Image Sensors

The influence of pixel design on charge transfer, mainly on potential barrier and potential pocket, is investigated in this paper. By simplifying the interface region between the pinned photodiode (PPD) and the transfer gate (TG), an intuitive and simple method for analyzing the potential barrier and pocket is presented. Through TCAD simulations, the validity of the analysis method is verified, and the influence of some key dimension and process parameters in PPD pixel design on the potential barrier and pocket is clarified. The whole study help improve the understanding of the charge transfer limitation mechanism, and can achieve high charge transfer efficiency and low image lag noise in the PPD pixel design of CMOS image sensors (CISs).

Simulation-based study on characteristics of dual vertical transfer gates in sub-micron pixels for CMOS image sensors

Recently dual vertical transfer gates (VTGs), used in sub-micron pixels with full-depth deep-trench isolation (FDTI), have demonstrated superior performance in CMOS image sensors such as improvement of full well capacity (FWC) and charge transfer, as compared to a single VTG. In this work, we investigate characteristics of both pixel schemes based on two design examples, which is carried out using extensive 3D TCAD simulation and automated multi-objective optimization flow with various photodiode implantation conditions satisfying certain design specifications. Simulation results reveal that dual VTGs better control electrostatic potentials along the charge transfer path like a 3D fin-shaped transistor. The enhanced gate controllability also makes the VTG off potential insensitive to the nearby doping concentrations, which is not the case for the single VTG pixel, and thus provides more room for boosting FWC in the photodiode design according to the Pareto front analysis.

Analytical Modeling of Potential Barrier for Charge Transfer in Pinned Photodiode CMOS Image Sensors

A potential barrier is one of the most common lag sources for charge transfer in pinned photodiode (PPD) CMOS image sensors (CISs). In this article, an analytical model of the potential barrier is proposed for the PPD combined with the transfer gate (TG). Through detailed electrostatic analysis of the PPD and TG, the potential barrier is analytically expressed as a function of the doping concentrations, TG voltage, spatial dimensions, and other physical parameters. The proposed model is validated by technology computer-aided design (TCAD) simulations, and the results show that the model data are in good agreement with the TCAD simulations in terms of the magnitude and location of the potential barrier. The model can be used for the design, simulation, and optimization of PPD-based pixels in CISs to improve the charge transfer efficiency (CTE) and reduce the image lag noise.

Design and Characterization of Near-Infrared Sensitivity-Enhanced Three-Tap Fully Depleted Image Sensor for Fluorescence Lifetime Imaging

A backside illumination (BSI) silicon-based CMOS image sensor (CIS) with three transfer gates is designed and optimized for near-infrared (NIR) fluorescence lifetime imaging microscopy (FLIM) applications. A three-tap design is considered for a more efficient fluorescence acquisition, avoiding sample damage and photobleaching. A thick silicon substrate and a p-well funnel are applied to obtain better external quantum efficiency (EQE) and lower parasitic light sensitivity (PLS) in the NIR range. In addition, the photocharge collection speed of the pixel is investigated and optimized. This three-tap image sensor performs a high EQE of 42.6% and a low PLS of −60 dB at 940 nm and a pixel response of 7.41 ns. Fluorescence lifetime imaging with a developed image sensor is demonstrated with accuracy as an example with the 705-nm peak emission.

Optimization of Photodiode Design Through Analysis of Full-Well Capacity and Image Lag in 0.5 μm CMOS Image Sensors With Vertical Transfer Gates

Recently, the main issue for developing the latest small pixels is maintaining the full-well capacity (FWC) while minimizing image lag as the pixel pitch is scaled down within the sub-micron scale. In this letter, the FWC and image lag characteristics are optimized by varying the photodiode (PD) doping profiles in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.5~\mu \text{m}$ </tex-math></inline-formula> CMOS image sensors with vertical transfer gates (VTGs) for the first time. Measurements and simulated results of various pitch generations are correlated to propose the most desirable PD doping conditions for <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.5~\mu \text{m}$ </tex-math></inline-formula> pixels which have not been developed yet. As a result, the ceiling position of the top PD doping significantly affects the image lag characteristics resulting in the lowest image lag when increasing the ceiling by 30% from the initial position. In conclusion, a fruitful guideline for photodiode design in 3D active pixel sensors is provided for optimization of FWC and image lag in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.5~\mu \text{m}$ </tex-math></inline-formula> pixel pitches. Also, this methodology associating potential curve analysis can be of potential use for development in ultra-small pixel pitches in the near future.

Novel Memristor-based Non-volatile D Latch and Flip Flop Designs

Abstract: Serial devices are the fundamental building elements of all digital electronic systems with memory. The non-volatile quality of sequential devices is necessary for quick data recovery after unexpected data loss, such as an unintentional power outage, which has sparked ongoing research and development into integrating a non-volatile memristor into CMOS devices. In this article, we examine using this technique to raise the caliber of nonvolatile D-latch. One memristor, a few transfer gates, and CMOS transducers are the sole components of the proposed D-latch, which sets it apart from conventional designs. Our design minimizes the negative impact of transistor threshold loss. In addition, a variety of memristor threshold values are available with our design

Hybridized bands and stacking-dependent band edges in ferromagnetic Fe3GeTe2/CrGeTe3 moir\xe9 heterobilayer

Owing to unique fundamental physics and device applications, twisted moiré physics in two-dimensional (2D) van der Waals (vdW) layered magnetic materials has recently received particular attention. We investigate magnetic vdW Fe3GeTe2 (FGT)/CrGeTe3 (CGT) moiré heterobilayers with twist angles of 11° and 30° from first-principles. We show that the moiré heterobilayer is a ferromagnetic metal with an n-type CGT layer due to the dominant spin-majority electron transfer from the FGT layer to the CGT layer, regardless of various stacked structures. The spin-majority hybridized bands between Cr and Fe bands crossing the Fermi level are found regardless of stacking. The band alignment of the CGT layer depends on the effective potential difference at the interface. We show that an external electric field perpendicular to the in-plane direction modulates the interface dipole and band edges. Our study reveals a deeper understanding of the effects of stacking, spin alignment, spin transfer, and electrostatic gating on the 2D vdW magnetic metal/semiconductor heterostructure interface.

Parasitic Coupling in 3D Sequential Integration: The Example of a Two-Layer 3D Pixel

In this paper, we present a thorough analysis of parasitic coupling effects between different electrodes for a 3D Sequential Integration circuit example comprising stacked devices. More specifically, this study is performed for a Back-Side Illuminated, 4T–APS, 3D Sequential Integration pixel with both its photodiode and Transfer Gate at the bottom tier and the other parts of the circuit on the top tier. The effects of voltage bias and 3D inter-tier contacts are studied by using TCAD simulations. Coupling-induced electrical parameter variations are compared against variations due to temperature change, revealing that these two effects can cause similar levels of readout error for the top-tier readout circuit. On the bright side, we also demonstrate that in the case of a rolling shutter pixel readout, the coupling effect becomes nearly negligible. Therefore, we estimate that the presence of an inter-tier ground plane, normally used for electrical isolation, is not strictly mandatory for Monolithic 3D pixels.