Abstract

This article presents an evaluation of the CMOS logic performance of a junctionless (JL) forksheet based on 3-D numerical simulation. The study investigates the transfer characteristics and gate capacitance of the JL-forksheet with channel doping ranging from <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{1}\ttimes\text{10}^{\text{19}}$</tex-math> </inline-formula> to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{6}\ttimes\text{10}^{\text{19}}/\text{cm}^{\text{3}}$</tex-math> </inline-formula> , to determine the optimal performance of the device. Results show that due to its lower gate capacitance, the JL-forksheet has a lower intrinsic delay than the IM-forksheet. Moreover, the JL-forksheet demonstrates improved logic performance in terms of rise time, fall time, propagation delay, and maximum oscillation frequency, with improvements of at least 25%, 35%, 17%, and 21%, respectively, as compared to the IM-forksheet. Based on its simple fabrication process, better power efficiency, and improved digital logic performance at the sub-2 nm technology node (N2), the JL-forksheet exhibits strong potential as a high-performance CMOS logic solution in the post-Moore era.

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