Abstract
A potential barrier is one of the most common lag sources for charge transfer in pinned photodiode (PPD) CMOS image sensors (CISs). In this article, an analytical model of the potential barrier is proposed for the PPD combined with the transfer gate (TG). Through detailed electrostatic analysis of the PPD and TG, the potential barrier is analytically expressed as a function of the doping concentrations, TG voltage, spatial dimensions, and other physical parameters. The proposed model is validated by technology computer-aided design (TCAD) simulations, and the results show that the model data are in good agreement with the TCAD simulations in terms of the magnitude and location of the potential barrier. The model can be used for the design, simulation, and optimization of PPD-based pixels in CISs to improve the charge transfer efficiency (CTE) and reduce the image lag noise.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
