Transconductance Frequency Product Research Articles

Source pocket engineered underlap stacked-oxide cylindrical gate tunnel FETs with improved performance: design and analysis

The effects of stacked SiO2/HfO2 gate oxide, source pocket, and underlap gate engineering on the electrical and RF performances of cylindrical gate tunnel field-effect transistors (CGTFETs) have been investigated in this paper. While source pocket with underlap engineering reduces both the gate leakage current and subthreshold swing (SS), the stacked gate oxide improves the drain current of the CGTFET. The DC and RF performance parameters such as the electric field, drain current, transconductance, gate capacitance, unity gain cut-off frequency, gain–bandwidth product, transconductance frequency product, and intrinsic delay have been investigated for different stacked oxide CGTFETs with and without a source pocket as well as with and without an underlap structure. Our study demonstrates that the proposed underlapped stacked-oxide source-pocket engineered CGTFET structure not only enhances the drain current, but also improves the subthreshold switching characteristics of the device by reducing SS and gate leakage current.

Investigation of Recessed Junctionless Double Gate MOSFET for Radio Frequency Applications

Junctionless Metal Oxide Semiconductor Field-Effect Transistor (JL MOSFET) is one of the promising candidate to replace the junction based MOSFET for upcoming technology nodes. Semiconductor industries are continuously urging for large ON current with the low OFF current and low specific on resistance. However, high ON current is achieved in Conventional (Conv.) JL DG MOSFET by using high doping concentration at the cost of high OFF current which leads depletion mode operation. Moreover, low doping, narrow channel thickness and high work function gate materials are using to operate Conv. JL DG MOSFET in enhancement mode (Vth > 0 V for N-JL DG MOSFET, Vth < 0 V for P-JL DG MOSFET) but ON current is reduced in all above mentioned solutions. To overcome the above mentioned problems, a new architecture is developed called Recessed JL DG MOSFET. In Recessed JL DG MOSFET silicon region is recessed under the gate region and some gate portion is extended towards source and drain region. Recessed JL DG MOSFET shows the same ON current as achieved in Conv. JL DG MOSFET with very low OFF current (leakage current) by considering high doping concentration. Surface potential, electron density, energy band distribution, drain current have been investigated to proof the enhancement mode operation of Recessed JL DG MOSFET. Figure of Merits (FOMs) for RF performance such as Trans-conductance, capacitance and intrinsic power gain (S21), Trans-conductance frequency product (TFP), Gain frequency product (GFP) and Gain trans-conductance frequency product (GTFP) have also investigated of Recessed JL DG MOSFET.

Investigation of Short Channel Effects (SCEs) and Analog/RF Figure of Merits (FOMs) of Dual-Material Bottom-Spacer Ground-Plane (DMBSGP) FinFET

FinFETs are popular and forefront runner in integrated circuits (ICs) technology due to exceptional scalability and suppressed short channel effects (SCEs). The bottom spacer (BP) concept is adopted in FinFET to achieve ameliorated short-channel, reduced self heating issues and to solve width quantization effect. The dual-material-gate (DMG) concept provides novel features like threshold voltage roll-up, transconductance enhancement and suppression of SCEs by work function engineering. Further, the ground-plane (GP) concept is also introduced to minimize the interaction between source and drain region which results in suppressed drain induced barrier lowering (DIBL). This paper investigates the systematic analysis of novel DMBSGP FinFET. The electrical performance parameters are extracted for different bottom spacer height (BSH) and workfunction differences (∆W). The analog/RF figure of merits (FOMs) such as transconductance (gm), output conductance (gd), transconductance generation factor (gm/ID), early voltage (VEA), intrinsic gain (AV), cut-off frequency (fT), transconductance frequency product (TFP), gain frequency product (GFP) and gain transconductance frequency product (GTFP) are examined for different BSH of DMBSGP FinFET using 3-D ATLAS device simulator.

Effect of air spacer in underlap GAA nanowire: an analogue/RF perspective

Here, a comprehensive study of the gate-all-around silicon nanowire field effect transistor (FET) (GAA-SNWTs) with source/drain underlap is performed to investigate the influence of air as spacer dielectric, on analogue/RF behaviour of the device. Parasitic capacitances in nanoscale devices contribute a dominating role in overall device capacitances. Introducing air as spacer dielectric () in source/drain underlap region, device parasitic capacitances deteriorates, which improves the overall capacitances. Thus, the analogue/RF figure-of-merit (FOM) of the device enhances, rendering the device suitable for low-power high-frequency operations. For targeting low power applications, FOMs are elicited at . It is perceived that intrinsic gain of the device is almost unaltered for distinct spacer dielectric ( and air). Frequencies like cut-off frequency () and maximum oscillation frequency () of air spacer dielectric-based underlap GAA-SNWTs are enhanced by 2.92 times and 3.11 times, respectively, when contrasted by the spacer-based GAA-SNWTs. This results in higher percentage improvement in RF-FOM in terms of transconductance frequency product (TFP), gain-frequency product (GFP), and gain transconductance frequency product (GTFP).

Optimization of ferroelectric tunnel junction TFET in presence of temperature and its RF analysis

This paper proposes a device incorporating ferroelectric tunnel junction which analyzes the concept of tunneling across a silicon doped hafnium oxide ferroelectric. Variation of electrical parameters with ferroelectric thickness has been examined. Subthreshold swing (SS) of 40 mV/dec has been achieved with ferroelectric thickness of 2 nm. An increasing trend in the ION/IOFF ratio is observed with the increase in ferroelectric thickness. Moreover, the impact of temperature (300 K–500 K) on drain current as well as various RF parameter performance such as gate capacitance (CGG), transconductance (gm), output conductance (gd), intrinsic delay, intrinsic gain (gm/gd), cut off frequency (ft) and transconductance frequency product (TFP) has been studied.

Analysis of non-uniform hetero-gate-dielectric dual-material control gate TFET for suppressing ambipolar nature and improving radio-frequency performance**Project supported by the University Natural Science Research Key Project of Anhui Province, China (Grant No. KJ2017A502), the Introduced Talent Project of Anhui Science and Technology University, China (Grant No. DQYJ201603), the Excellent Talents Supporting Project of Colleges and Universities, China (Grant No. gxyq2018048), and

A tunnel field-effect transistor (TFET) is proposed by combining various advantages together, such as non-uniform gate–oxide layer, hetero-gate-dielectric (HGD), and dual-material control-gate (DMCG) technology. The effects of the length of non-uniform gate–oxide layer and dual-material control-gate on the on-state, off-state, and ambipolar currents are investigated. In addition, radio-frequency performance is studied in terms of gain bandwidth product, cut-off frequency, transit time, and transconductance frequency product. Moreover, the length of non-uniform gate–oxide layer and dual-material control-gate are optimized to improve the on-off current ratio and radio-frequency performances as well as the suppression of ambipolar current. All results demonstrate that the proposed device not only suppresses ambipolar current but also improves radio-frequency performance compared with the conventional DMCG TFET, which makes the proposed device a better application prospect in the advanced integrated circuits.

Design Considerations and Capacitance Dependent Parametric Assessment of Gate Metal Engineered SiNW MOSFET for ULSI Switching Applications

This work investigates design consideration of Gate Electrode Workfunction Engineered (GEWE) silicon nanowire MOSFET at room temperature. It is perceived from the results that the parasitic capacitances are higher in the deep inversion region, however; the coupling of parasitic capacitance is weak in GEWE-SiNW due to lower gate metal workfunction at the drain end. Moreover, the influence of drain voltage on Cgs is very less owing to constant depletion charges at the source side which results in almost constant value of Cgs with the change in Vds. With tuning of channel length (Lg) and oxide thickness (tox), the effect of capacitances in GEWE-SiNW further reduces significantly due to quantization effect at such scaled dimensions. Furthermore, Transconductance Frequency Product (TFP), Energy Delay Product (EDP) and Gain Bandwidth Product (GBP) have also been calculated with an aim to analyze the device DC and switching performance as they are directly or indirectly linked with parasitic capacitance. Calibrated 3D simulations validate that the GEWE-SiNW MOSFET exhibit 2.57, 34.5 and 2.75 times improvement in TFP, EDP and GBP respectively in comparison to SiNW in the linear region.

Reduction of the kink effect in a SELBOX tunnel FET and its RF/analog performance

The kink effect in a fully depleted silicon-on-insulator (SOI) tunnel field-effect transistor (TFET) is studied and compared with the results for a SOI metal–oxide–semiconductor field-effect transistor (MOSFET) using a model that is calibrated against experimental results available in literature. A technique for eliminating the kink effect is proposed. The structure with a small gap in the buried oxide, known as the selective buried oxide (SELBOX) structure, is capable of reducing the kink effect. The impact of the kink effect on the device performance for different gap positions, thicknesses, and buried oxide thicknesses is examined. A better current–voltage characteristic is obtained for a position of the gap near the source. The effect of varying the temperature and the presence of a uniform trap charge on the kink effect for the SOI TFET, SOI MOSFET, and SELBOX structures is also studied. Various electrical parameters such as the subthreshold swing and ION/IOFF ratio are investigated for the TFET in the presence and absence of uniform trap charge. Although the SELBOX structure can minimize the kink effect, it is still present for such devices with narrow and wider gaps. Therefore, the gap thickness is optimized based on technology computer-aided design (TCAD) simulations. Furthermore, radio frequency (RF)/analog performance parameters such as the transconductance (gm), cutoff frequency (ft), transconductance generation factor (TGF = gm/ID), transconductance frequency product, gain transconductance frequency product, and 1-dB compression point are investigated using TCAD simulations and compared between the SELBOX MOSFET and SELBOX TFET devices.

Insights into the DC, RF/Analog and linearity performance of vertical tunneling based TFET for low-power applications

The concept of dual metal and double gate in Vertical TFET is presented to show the improvement of DC as well as analog/RF device performance standards due to enhanced gate modulation is presented in this work. This study includes the analysis of capacitances present in the device and various figures of merit (FOMs) such as transconductance (gm), cut-off frequency (fT), gain bandwidth product (GBP), transit time (τ) and transconductance frequency product (TFP) that is crucial in understanding the behavior of device for RF applications. Further from analog design point of view, it is intuitive that estimation of linearity is essential for accessing the scope of application of device. So, linearity and reliability is computed concerning higher order transconductance and VIP3, IIP3, IMD3 and 1-dB compression point of the device. The proposed TFET follows the ITRS roadmap for low standby power switch performance.

Temperature analysis of underlap GAA-SNWTs for analog/RF applications

In the present work, a comprehensive study of temperature on gate-all-around silicon nanowire FETs (GAA-SNWTs) with source/drain underlap is performed to investigate the influence of Air as spacer dielectric, on analog/RF behavior of the device. The transconductance gm of the device enhances when the temperature is dropped down to 100 K. Thus, the analog/RF figure-of-merit (FOM) of the device enhances, rendering the device suitable for low temperature, low-power high-frequency operations. For targeting low power applications, FOMs are elicited at 10 μA/μm. It is perceived that the intrinsic gain of the device is marginally altered for distinct spacer dielectric (Si3N4 and air). Frequencies like cut-off frequency (fT) and maximum oscillation frequency (fMAX) of air spacer dielectric based underlap GAA-SNWTs are enhanced by 2.15 times and 1.73 times respectively when the operating temperature is dropped down to 100 K from 400 K. This results in higher percentage improvement in RF-FOM in terms of transconductance frequency product (TFP), gain-frequency product (GFP), and gain transconductance frequency product (GTFP).

Investigation of RF and linearity performance of electrode work‐function engineered HDB vertical TFET

This work realises a hetero-dielectric buried oxide vertical tunnel held effect transistor (HDB VTFET) and investigates its radio frequency (RF) and linearity characteristics. First time, the concept of hetero-dielectric buried oxide (BOX) in VTFET is used to obtain the superior improvement in terms of different RF and linearity hgure of merits such as C gs , C gd , C gg , f T , Gain Bandwidth Product (GBP), t, Transconductance Frequency Product (TFP), Transconductance Generation Factor (TGF), g m2 , g m3 , VIP 2 , VIP 3 , IIP 3 , IMD 3 and 1-dB compression point. Also, the influence of HfO2 BOX length scaling on these FOMs is analysed. The results reveal that the HDB VTFET can be a promising contender to replace bulk metal-oxide semiconductor held-effect transistors in analogue/mixed signal system-on-chip and high-frequency microwave applications and the accuracy of this device is validated by TCAD Sentaurus simulator.

Analysis and performance exploration of high performance (HfO2) SOI FinFETs over the conventional (Si3N4) SOI FinFET towards analog/RF design

Nowadays FinFET devices have replaced the MOS devices almost in all complex integrated circuits of electronic gadgets like computer peripherals, tablets, and smartphones in portable electronics. The scaling of FinFET is ongoing and the analog/RF performance is most affected by increased SCEs (short channel effects) in sub 22 nm technology nodes. This paper explores the analog/RF performance study and analysis of high performance device-D2 (conventional HfO2 spacer SOI FinFET) and device-D3 (source/drain extended HfO2 spacer SOI FinFET) over the device-D1 (conventional Si3N4 spacer SOI FinFET) at 20 nm technology node through the 3-D (dimensional) simulation process. The major performance parameters like Ion (ON current), Ioff (OFF current), gm (transconductance), gd (output conductance), AV (intrinsic gain), SS (sub-threshold slope), TGF = gm/Id (trans-conductance generation factor), VEA (early voltage), GTFP (gain trans-conductance frequency product), TFP (tans-conductance frequency product), GFP (gain frequency product), and fT (cut-off frequency) are studied for evaluating the analog/RF performance of different flavored SOI FinFET structures. For analog performance evaluation, device-D3 and D2 give better results in terms of gm, ID (drain current) and SS parameters, and for RF performance evaluation device-D1 is better in terms of fT, GTFP, TFP, and GFP parameters both at low and high values of VDS = 0.05 V and VDS = 0.7 V respectively.

Temperature effect on RF/analog and linearity parameters in DMG FinFET

We systemically investigated the impact of variation in temperature on electrical parameters for a dual material gate (DMG) FinFET. We have highlighted the DC performance such as drain current characteristics, subthreshold swing (SS), and Ion/Ioff for the variation in temperature from 200 to 350 K. Furthermore, the influence of temperature on RF/Analog parameters like transconductance (gm), output conductance (gd), gate capacitance (CGG), intrinsic delay, transconductance generation factor (TGF = gm/ID), intrinsic gain (gm/gd), cutoff frequency (ft), gain frequency product (GFP), transconductance frequency product (TFP), and gain transconductance frequency product (GTFP) are presented through TCAD simulator. We also discussed the influence of temperature on linearity parameters like gm2, gm3, VIP2, VIP3, IMD3, IIP3, and 1-dB compression point. A comparative study between DMG and single material gate (SMG) FinFET is also investigated.

A Two-Dimensional (2D) Analytical Modeling and Improved Short Channel Performance of Graded-Channel Gate-Stack (GCGS) Dual-Material Double-Gate (DMDG) MOSFET

A Double-gate (DG) metal-oxide-semiconductor field effect transistor (MOSFET) is emerging device architecture in sub-nanometer regime. The performance of DG MOSFET can be ameliorated by gate and channel engineering. The concept of graded-channel gate-stack (GCGS) and dual-material (DM) are incorporated in DG MOSFET. A two-dimensional (2D) analytical surface potential model for GCGS DMDG MOSFET is developed based on the solution of Poisson’s equations with appropriate boundary conditions. It has been found that analytically modeled data is in good degree of agreement with numerically simulated data. The combination of both DM and GC concept introduces a step variation in potential profile at the junction of both materials in channel region and ameliorates the short channel effects (SCEs). A suppressed subthreshold swing (SS) and drain induced barrier lowering (DIBL) has been observed in the device due to an elevated average velocity of carrier and reduced drain field effect by the use of DM and GC with GS. Further, analog/RF characteristics such as transconductance generation factor (TGF), cut-off frequency (fT) and transconductance frequency product (TFP) have been examined with different GS high-k dielectrics. The numerically simulated data has been extracted using 2D ATLAS device simulator.

Surface Potential Modeling of Graded-Channel Gate-Stack (GCGS) High-K Dielectric Dual-Material Double-Gate (DMDG) MOSFET and Analog/RF Performance Study

In each complementary metal-oxide-semiconductor (CMOS) technology generation, design of new device architectures at nanoscale regime becomes quite challenging task due to increased short channel effects (SCEs) and leakage current. A double-gate (DG) MOSFET is an alternative structure. To enhance the performance of DG MOSFET, gate stack (GS) and dual-material gate (DMG) with graded-channel (GC) concepts are amalgamated. Analytical surface potential modeling of GCGS DMDG MOSFET has been done by solving the two-dimensional (2D) Poisson’s equation with suitable boundary conditions. The surface potential profile of GCGS DMDG MOSFET shows a step variation at the interface of two materials. The electrical parameters drain induced barrier lowering (DIBL), sub-threshold swing (SS) and on-current to off-current $\left (\frac {I_{on}}{I_{off}}\right )$ ratio reveals that, DMDG shows a better performance over single-material (SM) DG MOSFET with all (Si3N4, HfO2 and Ta2O5) GS high-k dielectric configurations. An enhanced performance in GCGS DMDG is due to the fact of increased average carrier velocity, reduced drain field effect and leakage current. Further, analog/RF performance parameters such as transconductance (gm), transconductance generation factor (TGF), cut-off frequency (fT), transconductance generation frequency product (TGFP), gain frequency product (GFP) and gain transconductance frequency product (GTFP) are extracted and compared for both SMDG and DMDG MOSFET with HfO2 GS configuration. The efficacy of analytically modeled results is compared with numerically simulated results obtained from 2D ATLAS device simulator.

Effect of Interface Trap Charges on Performance Variation of Heterogeneous Gate Dielectric Junctionless-TFET

In this paper, we investigate the effect of interface trap charges on the variation of heterogeneous gate dielectric junctionless-tunnel FET (JL-TFET) by introducing both donor and acceptor type of localized charges at the semiconductor/insulator interface. In this regard, we have analyzed dc and analog/RF performance parameters for conventional and heterogeneous gate dielectric JL-TFET (HD JL-TFET) in terms of electric field, transfer characteristics, transconductance ( ${g}_{m}$ ), output transconductance ( ${g}_{\text {ds}}$ ), parasitic capacitances, device efficiency, cutoff frequency ( ${f}_{T}$ ), gain bandwidth product, and transconductance frequency product. Apart from these, linearity distortion parameters are also analyzed in the form of higher order transconductance coefficients ( ${g}_{m1}$ , ${g}_{m2}$ , ${g}_{m3}$ ), VIP2, VIP3, IMD3, and IIP3. For this, high-K gate dielectric material (HfO2) is used in the case of the HD JL-TFET to improve the performance of the device. All the simulations for both devices have been performed with the help of an ATLAS device simulator.

Assessment of analog RF performance for insulated shallow extension (ISE) cylindrical surrounding gate (CSG) MOSFET incorporating gate stack

In this paper, insulated shallow extension cylindrical surrounding gate (ISE-CSG) MOSFET with high-k gate stack has been proposed and extensively investigated. The performance of high-k ISE-CSG MOSFET has been compared with cylindrical surrounding gate MOSFET. ISE-CSG with high-k gate stack has number of desirable features at 30 nm regimes. The results reveal that ISE-CSG MOSFET with gate stack is more immune to short channel effects because of improved carrier transportation capability. It has been observed that high-k ISE-CSG MOSFET shows improved figure of merits as drive current (ION), ION/IOFF ratio, transconductance (gm), cutoff frequency fT, transconductance generation factor, intrinsic gain (Av), transconductance frequency product, gain transconductance frequency product and gain frequency product. ISE-CSG with high-k gives better control over the depletion region and therefore it is a suitable device for high speed, high frequency and analog/RF circuit applications.

Investigation of parasitic capacitances of In2O5Sn gate electrode recessed channel MOSFET for ULSI switching applications

This work discusses the capacitance–voltage (C–V) analysis and frequency dependent capacitance of In2O5Sn (Tin Oxide) gate electrode Recessed Channel (TGRC) MOSFET with an aim to examine the effectiveness of In2O5Sn (Transparent) as a gate material on parasitic capacitance which prominently influences the current driving capability and thus, the switching performance. Moreover, capacitance dependent parameters such as Transconductance Frequency Product (TFP), Energy Delay Product (EDP) and Gain Bandwidth Product (GBP) are also assessed and found that, TFP increases to 6.33 times in comparison to metal gate RC MOSFET owing to a noticeable reduction in parasitic capacitance (Cgg = Cgs + Cgd), due to which EDP and GBP also improve considerably and thus reflects its effectiveness in RF amplifiers and receivers. In addition, the effect of parameter variation such as gate length (Lg) and negative junction depth (NJD) of TGRC is also observed, and results reveal that with Lg = 20 nm and NJD = 5 nm, TGRC unveils outstanding switching performance which is desirable for low power ULSI applications.

Improved analog and AC performance with increased noise immunity using nanotube junctionless field effect transistor (NJLFET)

In this paper for the first time, the noise immunity and analog performance of nanotube junctionless field effect transistor (NJLFET) has been investigated. Small signal AC performance metrics namely Scattering parameters (S-parameters) have been analyzed along with analog parameters to validate the suitability of NJLFET for RFIC design. NJLFET performance is examined by comparing its performance with junctionless gate-all-around (JLGAA) MOSFET. It has been inferred that NJLFET has improved I on/I off ratio directing improved digital performance at higher channel lengths, reduced channel resistance (R ch) which enables the MOSFET to provide a low resistance path to current and improved early voltage (V EA) which shows the capability for high-gain amplification and higher g m/g d directing high intrinsic dc gain. Higher f Tmax for NJLFET has been observed posing its potential for terahertz applications. Higher gain transconductance frequency product makes NJLFET an ultimate device for high-speed switching applications. Higher maximum transducer power gain in NJLFET implies higher power gain than JLGAA MOSFET. Also, NJLFET exhibits lower harmonic distortion and it has been explained by significant reduction in third-order derivative of transconductance, g m3. Reduction in g m3 shows that NJLFET provides better linearity over JLGAA and is more suitable for RFIC design. Also the S-parameters namely S11, S12, S21 and S22 have been analyzed to verify the small signal performance. A lower magnitude for reflection coefficients S11 and S22 depicts minimum reflection and higher matching between ports in NJLFET than JLGAA MOSFET. Higher voltage gains S12 and S21 are present in NJLFET than its counterpart which shows the higher gains that can be achieved using nanotube architecture. The noise metrics which are noise figure and noise conductance show significant reduction for NJLFET justifying its noise immunity.

Analog and RF performance of a multigate FinFET at nano scale

In this paper, analog and RF performance of the Fin field effect transistor (FET) at Nano scale is observed through 3D simulation. FinFET devices like rectangular gate all around (RE-GAA) FinFET, cylindrical gate all around (CY-GAA) FinFET and triple gate (TG) FinFET are observed. The figure of merit (FOMs) such as input-output characteristics, trans-conductance (gm), output-conductance (gd), intrinsic gain (gm/gd), gate capacitance (gate to source and total gate capacitance), unity gain cut-off frequency (ft), trans-conductance generation factor (TGF), gain frequency product (GFP), gain bandwidth product (GBP) and gain transconductance frequency product (GTFP) are observed. The analog performance of a FinFETs are observed by realising source follower circuit with NMOS transistor as a current source. The source follower circuit gain is observed. It has been observed that maximum capacitance is observed in case gate all around condition. Rectangular gate all around has the highest transconductance. In the source follower circuit, the gain curve (Vout/Vin) is sharper for TG-FinFET.