TLP Test Research Articles

Design of a LVTSCR triggered SCR device for low voltage ESD protection

In this paper, a novel silicon-controlled rectifier (SCR) electrostatic discharge (ESD) protection device, called low voltage triggered SCR (LVTSCR) triggered SCR (LVTSCRTSCR), is proposed for 3.3 V I/O protection applications in 0.18 μm CMOS technology. One side of the device is the traditional LVTSCR structure, and other side is the traditional SCR structure. The two structures are connected by a floating P+ diffusion layer. The working principle of LVTSCRTSCR was verified by the TCAD simulation results and TLP test results. The test results show that the triggering voltage of LVTSCRTSCR is determined by the traditional LVTSCR, with a value of 9.850 V. The holding voltage of the device can be effectively improved by increasing the size of the floating diffusion layer D4. When D4 = 6 μm, the holding voltage can be 4.491 V, suitable for 3.3 V I/O.

Influence of cable length between TLP test system and DUT and its correction for CMCESD saturation measurement

Influence of cable length between TLP test system and DUT and its correction for CMCESD saturation measurement

Design, Fabrication and Measurement of LDNMOSSCR Devices with Appropriate ESD Protection Window for 18V HV CDMOS Process

LDMOS embedded SCR is a normal way to improve the ESD robustness for smart power technologies, but it doesn’t always have the proper ESD window for a given application. In this paper, LDNMOS-SCR of four variants structures have been inves-tigated based on a high-voltage (HV) 0.5μm 18V HV CDMOS process with 2D device simulation and silicon verification. TLP testing results demonstrated that those devices successfully elevate the second breakdown current I t2 from original 1.146A to above 3A; source isolated device has a lower V t1 (45.79V) than source non-isolated devices; the V h of the four devices is related to their structure, and their I h are all above 800mA, which is big enough to ensure the latch-up immunity under ESD stresses in HV applications. The device with its source isolated from PSUB is the suitable ESD protection device for HV 18V CDMOS technology owning to its strong ESD robustness, low V t1 , small R on and sufficiently big I h .

Design of GGNMOS ESD protection device for radiation-hardened 0.18 μm CMOS process

In this paper, the ESD discharge capability of GGNMOS (gate grounded NMOS) device in the radiation-hardened 0.18 μm bulk silicon CMOS process (Rad-Hard by Process: RHBP) is optimized by layout and ion implantation design. The effects of gate length, DCGS and ESD ion implantation of GGNMOS on discharge current density and lattice temperature are studied by TCAD and device simulation. The size of DCGS, multi finger number and single finger width of ESD verification structures are designed, and the discharge capacity and efficiency of GGNMOS devices in ESD are characterized by TLP test technology. Finally, the optimized GGNMOS is verified on the DSP circuit, and its ESD performance is over 3500 V in HBM mode.

A modified low voltage triggered silicon controlled rectifier (SCR) for ESD applications

In this paper, a modified low voltage triggered silicon-controlled rectifier (MLVTSCR) with low trigger voltage and high holding voltage has been proposed and implemented in both 28 nm CMOS process and 0.18 μm CMOS process. By segmenting the N+ active area bridged on the PW/NW junction of LVTSCR into blocks by P+ region, MLSCR was integrated into LVTSCR. The p+ blocks and the n+ blocks are alternately arranged and aligned in the same strip, in this way the proposed MLVTSCR is implemented. Without any extra mask as well as auxiliary trigger component, the proposed MLVTSCR possesses a very low trigger voltage and an adjustable high holding voltage from 2.05 to 4.29 V in 28 nm CMOS process and from 3.32 to 7.3 V in 0.18 μm BCD process under the TLP test, making it a superior candidate for electrostatic discharge protection in the 3.3 V/5 V CMOS processes. TCAD simulations has also been carried out to explore the intrinsic physical mechanisms of the proposed devices.

A Compact and Self-Isolated Dual-Directional Silicon Controlled Rectifier (SCR) for ESD Applications

In this paper, a compact and self-isolated dual directional silicon-controlled rectifier (CSDDSCR) developed in a single N-well has been proposed and demonstrated. Without using the P-well, the N-type isolation structure as well as an auxiliary trigger component, which are normally required in the traditional DDSCR, the novel CSDDSCR possesses a very high area-efficiency and robustness of ~8.81 V / $\mu$ m2. It is also shown that the CSDDSCR preserves a lower trigger voltage as 10 V, an adjustable holding voltage from 3.32 to 8.79 V under the TLP test, a smaller overshoot voltage of ~19 V at 2 A VFTLP stress, as well as an extremely low leakage current of ~94 pA measured at 3.3 V, making it a superior candidate for electrostatic discharge protection in the 3.3 V/5 V CMOS processes. Moreover, a holding voltage reversal effect has also been discovered and explained with TCAD simulation.

Validity Evidence of the Test of Word Reading for Portuguese Elementary Students

Abstract. This article presents data concerning the validity evidence of a test of word reading (TLP – Teste de Leitura de Palavras) that assesses single-word reading accuracy in Portuguese students from Grades 1 to 4. The test is composed of four vertically scaled forms, one for each grade, allowing for the evaluation of students’ word reading progression. In the internal structure-related evidence validity study, administration of the TLP to 905 Portuguese elementary students confirmed its one-dimensional structure. In the evidence based on the relationship with other variables’ study, 280 Portuguese elementary students were assessed with each TLP test form and criterion measures (reading tests, digit span, and vocabulary measures). Significant correlations were observed between results from the TLP test forms, reading instruments, short-term memory, and vocabulary measures. These results revealed adequate evidence based on internal structure and evidence based on the relationship to other variables of the TLP for the assessment of word reading accuracy in Portuguese elementary students.

Failure analysis of ESD-stressed SiC MESFET

Reliability studies are required for SiC device development. In a previous work we studied the intrinsic ESD robustness of a SiC MESFET. The failure mechanism was related to the triggering of an NPN parasitic transistor. In this work, a new MESFET layout is considered, which optionally include a Zener diode for internal protection. TLP testing and failure analysis has been carried out. Two new failure mechanisms are evidenced. Based on this knowledge, solutions are proposed to further improve the ESD robustness.

Anti-ESD Improvement of a Power nLDMOS with a Perpendicular Super-Junction Construction in the Drain Side

An HV 60-V nLDMOS by adding a perpendicular-type super-junction (SJ) structure and changing pillar widths in the drain side will be investigated in this paper. In order to verify some physical parameters influences on the ESD capability, a TLP testing equipment will be used for obtaining the secondary breakdown current (It2) in different DUTs. In It2values comparison, an SJ-nLDMOS is higher than that of a traditional nLDMOS, and as the pillar width increased the equivalent HBM value can be up to 4.799-kV. Finally, from the relationship between the SJ-nLDMOS and Ref. DUT, it can be found that an SJ structure is good for ESD discharge, as compared with the Ref. group can be increasing by 25%. In addition, the Vt1and Vhvalue of various kinds of SJ-nLDMOS will decline than the traditional nLDMOS.

Stacked zener trigger SCR for HV IC ESD protection

In HV BCD technology, SCR cannot been directly used as ESD protection owing to its high trigger voltage and low holding voltage. Stacked zener trigger SCRs for HV ESD protection is proposed and Compared to the traditional SCR. The proposed devices are fabricated with 0.35um BCD process on P-type bulk wafers without buried layer. TLP testing results show that the single zener trigger SCR with 50um width has a 6.7V trigger voltage and 4.1A failure current It2. Stacked 4 zener trigger SCRs is designed for 24V I/O ESD protection, which has 8V holding voltage, 27V trigger voltage and pass7KV HBM.

ESD performance of LDMOS with source-bulk layout structure optimization

To enhance the robustness of LDMOS ESD protection devices, the influence of a source-bulk layout structure is analyzed by theoretical analysis and numerical simulation. Novel structures with varied source-bulk layout structures are fabricated and compared. As demonstrated by TLP testing, the optimized structure has an 88% larger It2 than a conventional one, and its Vt1 is reduced from 55.53 to 50.69 V.

Test and Analysis of the ESD Robustness for the Diode-Connected a-IGZO Thin Film Transistors

In this work, wafer level TLP testing is applied to amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs) to study the factors of their electrostatic discharge (ESD) robustness. Two kinds of TFTs with N2O and O2 treatments are subject to the ESD test. It is found that the contact resistance of the TFTs, instead of the channel quality, dominates the ESD power for them to be damaged.

ESD characterization of a 190V LIGBT SOI ESD power clamp structure for plasma display panel applications

In this paper, ESD protection devices for power rails in a PDP scan IC are studied. By numerical simulation, current flow distribution of LIGBT under ESD stress is analyzed. The proposed latchup free LIGBT has additional discharge mechanism to optimize the discharge path, and much smaller discharge resistance can be obtained. As demonstrated by TLP test, optimized LIGBT has 33% larger It2 than HV diode, and its Vt2 is only 27V higher than its breakdown voltage.

Increasing substrate resistance to improve the turn-on uniformity of a high-voltage multi-finger GG-nLDMOS

With the impact of the non-uniform turn-on phenomenon, the ESD robustness of high-voltage multi-finger devices is limited. This paper describes the operational mechanism of a GG-nLDMOS device under ESD stress conditions and analyzes the reason that causes the non-uniform turn-on characteristics of a multi-finger GG-nLDMOS device. By means of increasing substrate resistance, an optimized device structure is proposed to improve the turn-on uniformity of a high-voltage multi-finger GG-nLDMOS. This approach has been successfully verified in a 0.35 μm 40 V BCD process. The TLP test results reveal that increasing the substrate resistance can effectively enhance the turn-on uniformity of the 40 V multi-finger GG-nLDMOS device and improve its ESD robustness.

Investigation of ESD protection strategy in high voltage Bipolar–CMOS–DMOS process

This paper presents device optimization and physical analysis based on gate-grounded NMOS (GGNMOS) and n-channel lateral DMOS (nLDMOS) devices manufactured in a 0.35μm 5V/30V high-voltage BCD process. The multiple body pick-up technique has been investigated in detail for the GGNMOS, and the robustness and effectiveness of the LDMOS device is optimized by tuning the drain contact to gate space (DCGS) and increasing the body resistance. Finally, the trigger voltage walk-in effect is observed for the nLDMOS device and is studied by comprehensive simulation and TLP tests.

A novel gate-suppression technique for ESD protection

A novel gate-suppression technique derived from source-pumping technique is proposed for Electrostatic Discharge (ESD) protection application. By employing the complementary SCR structure, an improved source-pumping and the gate-suppression scheme are able to extend ESD window and endure a high level of ESD impact without additional layout area cost. The fast rise time TLP test revealed the gate-suppression technique provide more effective protection than the source-pumping technique.

On-chip system level protection of FM antenna pin with improved linearity

An on-chip protection against IEC 61000-4-2 discharges is presented. The protection level is tested by means of HMM stress. The failure signature is identified by means of TLP testing and physical failure analysis. It is shown that it is possible to accurately predict the HMM failure level by means of a simplified circuit model, calibrated by means of 100 ns TLP data. A second version of the on-chip protection combines an improved linearity of the FM output with a superior ESD performance.

Effect of distances from source or drain to the gate on the robustness of sub-micron ggNMOS ESD protection circuit

In this paper,based on the research of the features about high voltage and high current under electrostatic discharge(ESD),the new 3D model of 0.6 μm gate-grounded NMOS(ggNMOS) ESD protection circuit with CSMC 6S06DPDM-CT02 CMOS technology have been derived from the optimization of lattice self-heating drift/diffusion model and its thermal model; systematic study about the effect of drain contact to gate spacing(DCGS)and the source contact to gate spacing(SCGS)on the relative protection circuit robustness index(turn-on voltage,breakdown voltage,self-heating peak,etc)have been done based on this model. The simulation results show that turn-on voltage and thermal balance are not influenced by the change of DCGS and SCGS,and compared to SCGS,DCGS is more sensitive to the breakdown voltage and the self-heating peak value of protection circuit. To improve the robustness of ESD protection circuit,it is not appropriate to monotonic increase the DCGS and SCGS for the reason that the breakdown voltage cannot be increased and the self-heating peak value of devices cannot be reduced by increasing DCGS and SCGS continuously. Compared to the TLP test results of 0.5 μm and 0.6 μm CMOS,a better reflection about the trend of electrical and heating features is derived from the simulation results,and the conclusions and test results are fully consistent. The reference for sub-micrometer ggNMOS ESD protection circuit layout parameter can be provided by the study.

Transient voltage overshoot in TLP testing – Real or artifact?

This paper investigates on the transient pulse response of the device under test, which is becoming a critical aspect in determining the ESD reliability of a variety of technology products. For the first time, the feasibility to calibrate or tune the artifacts arising out of system parasitic to ‘see’ the device transient response is presented in this paper with experimental data and numerical analysis.

Comprehensive ESD protection approach in advanced CMOS SOI technologies

In this paper we describe a 90 nm SOI ESD protection network and design methodology including both device and circuit level characterization data. We compare TLP results of SOI MOSFETs and diodes to bulk devices. We present a new response surface method to optimize device sizes in the ESD networks and show circuit level data comparing TLP test results and SPICE simulation results of an I/O test circuit. We also present product test data for standard ESD stress models.