Effect of distances from source or drain to the gate on the robustness of sub-micron ggNMOS ESD protection circuit

Abstract

In this paper,based on the research of the features about high voltage and high current under electrostatic discharge(ESD),the new 3D model of 0.6 μm gate-grounded NMOS(ggNMOS) ESD protection circuit with CSMC 6S06DPDM-CT02 CMOS technology have been derived from the optimization of lattice self-heating drift/diffusion model and its thermal model; systematic study about the effect of drain contact to gate spacing(DCGS)and the source contact to gate spacing(SCGS)on the relative protection circuit robustness index(turn-on voltage,breakdown voltage,self-heating peak,etc)have been done based on this model. The simulation results show that turn-on voltage and thermal balance are not influenced by the change of DCGS and SCGS,and compared to SCGS,DCGS is more sensitive to the breakdown voltage and the self-heating peak value of protection circuit. To improve the robustness of ESD protection circuit,it is not appropriate to monotonic increase the DCGS and SCGS for the reason that the breakdown voltage cannot be increased and the self-heating peak value of devices cannot be reduced by increasing DCGS and SCGS continuously. Compared to the TLP test results of 0.5 μm and 0.6 μm CMOS,a better reflection about the trend of electrical and heating features is derived from the simulation results,and the conclusions and test results are fully consistent. The reference for sub-micrometer ggNMOS ESD protection circuit layout parameter can be provided by the study.