Abstract
An on-chip protection against IEC 61000-4-2 discharges is presented. The protection level is tested by means of HMM stress. The failure signature is identified by means of TLP testing and physical failure analysis. It is shown that it is possible to accurately predict the HMM failure level by means of a simplified circuit model, calibrated by means of 100 ns TLP data. A second version of the on-chip protection combines an improved linearity of the FM output with a superior ESD performance.
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