Lifetime reliability modeling on EMC performance of digital ICs influenced by the environmental and aging constraints: A case study

Abstract

This paper aims to develop the lifetime reliability model on electromagnetic compatibility (EMC) performance of the Atmel Attiny85 microcontroller integrated circuit (IC) chip samples, depending on the observed variation of the conducted immunity to the electromagnetic interference imposed by the combined influence of various environmental and aging (i.e., thermal and electrical voltage stress) constraints. A constant-stress accelerated degradation tests plan was designed and implemented by applying different constant thermal (i.e., 70 and 110 °C) and electrical voltage (i.e., 4 and 5 V) stress magnitude levels simultaneously in various multiple stress combinations. Direct power injection (DPI) conducted immunity tests were performed in nominal condition on all the programmed device under test (DUT) samples in both the fresh and aged states at various stress time duration. The best-fit EMC degradation paths were generated using regression analysis, followed by evaluating the pseudo time-to-failure (TTF) data and estimating the unknown parameters of the developed degradation path model. The performance metrics for lifetime reliability were evaluated by combining the Weibull distribution function with the generalized Eyring accelerated life test model. The maximum likelihood estimation method was utilized to estimate the relevant reliability model parameters. The developed reliability model was found to have the capability to estimate the electromagnetic unreliability against the lifetime TTF data of all the selected DUT samples with good precision and acceptable accuracy in both nominal and aging stress conditions. It is demonstrated that the non-failure probability of the DUT samples would remain at 1 for the first 1200 h, and that, under nominal conditions, the prediction of corresponding TTF data for all of those IC samples would fluctuate between 1400 and 1600 h.