Design, Fabrication and Measurement of LDNMOSSCR Devices with Appropriate ESD Protection Window for 18V HV CDMOS Process

Abstract

LDMOS embedded SCR is a normal way to improve the ESD robustness for smart power technologies, but it doesn’t always have the proper ESD window for a given application. In this paper, LDNMOS-SCR of four variants structures have been inves-tigated based on a high-voltage (HV) 0.5μm 18V HV CDMOS process with 2D device simulation and silicon verification. TLP testing results demonstrated that those devices successfully elevate the second breakdown current I t2 from original 1.146A to above 3A; source isolated device has a lower V t1 (45.79V) than source non-isolated devices; the V h of the four devices is related to their structure, and their I h are all above 800mA, which is big enough to ensure the latch-up immunity under ESD stresses in HV applications. The device with its source isolated from PSUB is the suitable ESD protection device for HV 18V CDMOS technology owning to its strong ESD robustness, low V t1 , small R on and sufficiently big I h .