Investigation of ESD protection strategy in high voltage Bipolar–CMOS–DMOS process

Fei Ma,Yan Han,Shurong Dong,Meng Miao,Jianfeng Zheng,Jian Wu,Cheng-Gong Han,Kehan Zhu

doi:10.1016/j.microrel.2011.11.011

Investigation of ESD protection strategy in high voltage Bipolar–CMOS–DMOS process

Fei Ma, Yan Han + Show 6 more

https://doi.org/10.1016/j.microrel.2011.11.011

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Journal: Microelectronics Reliability	Publication Date: Dec 3, 2011
Citations: 2

Affiliation: Zhejiang University

#N-channel Lateral DMOS #High-voltage BCD Process + Show 8 more

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Abstract

This paper presents device optimization and physical analysis based on gate-grounded NMOS (GGNMOS) and n-channel lateral DMOS (nLDMOS) devices manufactured in a 0.35μm 5V/30V high-voltage BCD process. The multiple body pick-up technique has been investigated in detail for the GGNMOS, and the robustness and effectiveness of the LDMOS device is optimized by tuning the drain contact to gate space (DCGS) and increasing the body resistance. Finally, the trigger voltage walk-in effect is observed for the nLDMOS device and is studied by comprehensive simulation and TLP tests.

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