Time-to-digital Converter Resolution Research Articles

A Fully Synthesizable Fractional-N Digital Phase-Locked Loop with a Calibrated Dual-Referenced Interpolating Time-to-Digital Converter to Compensate for Process–Voltage–Temperature Variations

This paper presents advancements in the performance of digital phase-locked loop (DPLL)s, with a special focus on addressing the issue of required gain calibration in the time-to-digital converter (TDC) within phase-domain DPLL structures. Phase-domain DPLLs are preferred for their simplicity in implementation and for eliminating the delta–sigma modulator (DSM) noise inherent in conventional fractional-N designs. However, this advantage is countered by the critical need to calibrate the gain of the TDC. The previously proposed dual-interpolated TDC(DI-TDC) was proposed as a solution to this problem, but strong spurs were still generated due to the TDC resolution, which easily became non-uniform due to PVT variation, degrading performance. To overcome these problems, this work proposes a DPLL with a new calibration system that ensures consistent TDC resolution matching the period of the digitally controlled oscillator (DCO) and operating in both the foreground and background, thereby maintaining consistent performance despite PVT variations. This study proposes a DPLL using a calibrated dual-interpolated TDC that effectively compensates for PVT variations and improves the stability and performance of the DPLL. The PLL was fabricated in a 28-nm CMOS process with an active area of only 0.019 mm2, achieving an integrated phase noise (IPN) performance of −17.5 dBc, integrated from 10 kHz to 10 MHz at a PLL output of 570 MHz and −20.5 dBc at 1.1 GHz. This PLL operates within an output frequency range of 475 MHz to 1.1 GHz. Under typical operating conditions, it consumes only 930 µW with a 1.0 V supply.

Monolithic MHz-frame rate digital SiPM-IC with sub-100 ps precision and 70 μm pixel pitch

This paper presents the design and characterization of a monolithic integrated circuit (IC) including digital silicon photomultipliers (dSiPMs) arranged in a 32 × 32 pixel matrix at 70 μm pitch. The IC provides per-quadrant time stamping and hit-map readout, and is fabricated in a standard 150-nm CMOS technology. Each dSiPM pixel consists of four single-photon avalanche diodes (SPADs) sharing a quenching and subsequent processing circuitry and has a fill factor of 30 %. A sub-100 ps precision, 12-bit time-to-digital converter (TDC) provides timestamps per quadrant with an acquisition rate of 3 MHz. Together with the hit map, the total sustained data throughput of the IC amounts to 4 Gbps. Measurements obtained in a dark, temperature-stable environment as well as by using a pulsed laser environment show the full dSiPM-IC functionality. The dark-count rate (DCR) as function of the overvoltage and temperature, the TDC resolution, differential and integral nonlinearity (DNL/INL) as well as the propagation delays across the matrix are presented. With aid of additional peripheral test structures, the main building blocks are characterized and key parameters are presented.

Design and Implementation of Two-Stage Time-to-Digital Converter Based on Rapid Single-Flux-Quantum Circuits

This work proposed a new time-to-digital converter (TDC) utilizing rapid single-flux-quantum circuits. The proposed TDC architecture comprises a counter and a ring oscillator to construct a coarse TDC and a vernier delay line to build a fine TDC, which would maintain the high resolution and high dynamic range of the whole TDC. A TDC with the proposed architecture has been designed, fabricated, and successfully tested. The measurement shows that the designed TDC works correctly with a 5.5 ps resolution, a 1320 ps dynamic range, and a 1.5 LSB differential nonlinearity.

A Resolution Control Loop for TDC-Based Phase Detectors in ADPLLs

This paper proposes a resolution control loop that runs in background to control the time resolution of a mid-rise Time to Digital Converter (TDC) used as a phase detector in All-Digital Phase Locked Loops (ADPLLs). The proposed resolution control loop minimizes the TDC resolution until the TDC linear dynamic range equals the range of the input time error. Consequently, PLL in-band phase noise is reduced due to reduction of the Power Spectral Density (PSD) of the TDC quantization noise. Moreover, the linearity of the TDC transfer function across the range of the input time error is guaranteed. On contrary, the counterpart resolution control loop based on Lloyd-Max algorithm does not guarantee the linearity of the TDC transfer function across the range of the input time error. Furthermore, the proposed resolution control loop achieves TDC quantization noise with a lower variance compared to that achieved by the counterpart resolution control loop when applied with a TDC with more than 3 bits. Finally, the hardware implementation of the proposed resolution control loop is more area and power efficient compared to the implementation of the counterpart resolution control loop.

A 4.7-ps Resolution Recirculating Cyclic Vernier TDC Using DWA-Based Mismatch Correction and a Register-Based Time Amplifier

Herein, we present a recirculating (RC) cyclic Vernier time-to-digital converter (TDC) using dynamic element matching and a register-based time amplifier (TA). The RC TDC reuses a single conversion stage for multiple conversions that are suitable for low power and compact realization. Good matching is achieved between multiple conversions because the same stage is reused. Processing the amplified residue further enhances the TDC resolution. We propose a new TA based on a time register that achieves a well-controlled time magnification over a wide input range. Unlike conventional approaches based on regeneration or meta-stability, the register-based TA does not suffer from a narrow input range. The proposed TA achieves a relatively high gain accuracy (< 1.5%) over a wide input range from 40 to 400 ps. Compact TDC implementation is further facilitated using the multiphase operation of a gated ring oscillator (GRO) in a cyclic Vernier structure. Using the phase-preserving characteristic of the GRO, the mismatch is first order shaped by data weight averaging. The RC TDC fabricated using a 28-nm CMOS process is realized in a small area of 0.0096 mm2. Measurements show that the TDC can be successfully configured into four gain modes with a resolution of 11.5, 7.7, 5.8, and 4.7 ps in a 12-bit dynamic range. The full range linearity measurement shows an integral nonlinearity of less than 1.48 LSB. The power consumption is 0.188 mW at a conversion rate of 3.51 MHz, leading to a favorable figure of merit of 0.032 pJ/conv.-step. The results show the effectiveness of the RC structure in realizing a high-performance, compact TDC.

A high-precision time-to-digital converter applied to CDC

This paper presents a high-precision CMOS time-to-digital converter (TDC) applied to a capacitance-to-digital converter (CDC). The time-to-digital converter in the capacitance-to-digital converter is used to measure the time interval between the charging time of the capacitor under test and the charging time of the internal reference capacitor. The time resolution of the TDC directly determines the capacitance resolution of the CDC. In order to improve the measurement resolution of TDC, a TDC structure based on phase-locked loop (PLL) is proposed. This paper first gives a capacitance-to-digital converter scheme, and then introduces the time-to-digital converter used in the scheme. The frequency multiplication technology of the phase-locked loop optimizes the integral nonlinearity (INL) of the interpolator and greatly improves the interpolation of the interpolation ratio. The TDC was realized in a 0.13-μm CMOS process, and the measurable time interval is 21.14μs. When the external reference clock is 200MHz, the resolution is 40.3ps and only 31 delay units are needed.

Models of Direct Time-of-Flight Sensor Precision That Enable Optimal Design and Dynamic Configuration

Direct time-of-flight (dToF) sensors that measure depth by pulsing a laser and timing the photon return are used in many applications, including consumer electronics for proximity sensing and depth map generation. A histogram of photon return times is measured and then processed to estimate object depth. By collecting many photons that span multiple bins of the histogram the final depth estimate interpolates between time-to-digital converter (TDC) bins to produce a result that is more precise than the converter resolution. The precision of this interpolation depends on the temporal spread of the measurement, the resolution of the TDC, and the number of signal and background photons measured. There is a need for dToF depth precision models to guide design and predict and tune performance during use. In this article, we present models that estimate sensor depth precision versus dToF design parameters and photons measured. We use Monte Carlo simulations and experimental measurements to prove the accuracy of the models. With proven models in hand, we investigate a dToF sensor design by first presenting the dependence of precision upon the TDC resolution and the signal-to-noise ratio. Second, we experimentally measure the depth precision versus the intensity of background illumination. The models closely match the measurements of background susceptibility and locate a transition point of background intensity below which precision is constant and above which the precision continuously degrades. Finally, experimental measurements demonstrate how the modeling enables dynamic tuning: from a single histogram we estimate precision, thus enabling sensor exposure time tuning for a target precision or prediction of the precision given a change in object distance or background illumination. This work presents straightforward models verified by simulation and measurement. These models guide dToF design and enable dynamic adjustments that benefit power-constrained usage scenarios.

A 12-bit branching time-to-digital converter with power saving features and digital based resolution tuning for PVT variations

This paper presents a 12-bit branching Time-to-Digital converter (TDC) fabricated in a 40 nm CMOS technology. It composes of a 6-bit coarse counter TDC, and a 6-bit fine TDC. The fine TDC utilizes a proposed branching technique to interpolate between the phases of a 16-stage gated ring oscillator, increasing its number of phases from 16 to 64. Therefore, the TDC resolution is improved to be 4 times finer. The TDC incorporates fully digital based resolution tuning capability that enables its resolution to be more stable over PVT variations. Measurement results show that the resolution tuning reduces the resolution variation by 92.3% over a temperature range of − 40 to 125 °C. However, the simple resolution tuning method causes the TDC to have a relatively large resolution of 36.2 ps. The trade-offs between TDC resolution, yield, and scalability are discussed. The proposed TDC uses simple gated inverters based samplers instead of conventional arbiters to reduce power and area consumption. In addition, power gating features of the proposed TDC enable a low power consumption of 275 µW at a sampling rate of 5 MS/s. Without any linearity calibrations, the TDC DNL, INL, single-shot precision, and figure-of-merit are measured to be 1.30 LSB, 3.61 LSB, 0.75 LSB, and 61.9 fJ/conv.-step, respectively.

Implementation of 5.3 ps RMS precision and 350 M samples/second throughput time-to-digital converters with event sampling architecture in a Kintex-7 FPGA

Unlike the conventional field programmable gate array (FPGA) based time-to-digital converter (TDC) with clock sampling architecture, the TDC with event sampling architecture implemented in this paper propagates the system clock signal along the tapped-delay line (TDL) and the TDL status is sampled by a hit signal for time interpolation. Since there are several “1–0” and “0–1” transitions in the sampled TDL status, the TDC naturally realizes multiple measurements in parallel without increasing the resource consumption and the measurement dead time. Using a Xilinx Kintex-7 FPGA, we increase the number of equivalent TDC bins approximately to twice the number of physical delay cells in the TDL, which means the TDC resolution is about twice as good as the original. The average RMS precision is measured as 5.3 ps with two identical TDC channels measuring the time intervals in the range 0 to 20 ns. The proposed encoding scheme is so efficient that the TDC measurement throughput can reach 350 M samples per second. The test results show that the event sampling architecture is effective in FPGA as well. The performance that can be achieved is comparable with the performance of their counterparts that use the clock sampling architecture.

An 8.5-ps Two-Stage Vernier Delay-Line Loop Shrinking Time-to-Digital Converter in 130-nm Flash FPGA

A new time-to-digital converter (TDC) with high resolution and high precision is designed and tested in this paper. The converter is realized by combining coarse clock counter with a two-stage delay-line loop shrinking interpolator (DLLSI) based on Vernier configuration, and its prototype has been implemented in a low-cost flash field-programmable gate array device SmartFusion A2F200M3F (Actel). Delay-line loops are used to achieve differential Vernier delay unit and directly shrink the time interval. In order to improve the resolution, decrease measurement time, and diminish the jitter of the cyclic pulse, a two-stage DLLSI method is proposed. The first-stage interpolator rapidly shrinks the measured time interval with low resolution, and the second-stage interpolator determines the final fine resolution. The resolutions are dependent on the entire delay time differences between two delay-line loops of each interpolator. The optimal resolutions are theoretically calculated, and statistic code density test is used to estimate the resolution of the implemented TDC. The implemented two-stage DLLSI has achieved 8.5-ps resolution with 42.4-ps standard deviation and 10-ns dynamic range. The maximum integral and differential nonlinearity errors are less than 7.8 and 3.1 ps.

Toward Implementing Multichannels, Ring-Oscillator-Based, Vernier Time-to-Digital Converter in FPGAs: Key Design Points and Construction Method

For TOF positron emission tomography (TOF PET) detectors, time-to-digital converters (TDCs) are essential to resolve the coincidence time of the photon pairs. Recently, an efficient TDC structure called ring-oscillator-based (RO-based) Vernier TDC using carry chains was reported by our team. The method is very promising due to its low linearity error and low resource cost. However, the implementation complexity is rather high especially when moving to multi-channels TDC designs, since this method calls for a manual intervention to the initial fitting results of the compilation software. In this paper, we elaborate the key points toward implementing high performance multi-channels TDCs of this kind while keeping the least implementation complexity. Furthermore, we propose an efficient fine time interpolator construction method called the period difference recording which only needs at most 31 adjustment trials to obtain a targeted TDC resolution. To validate the techniques proposed in this paper, we built a 32-channels TDC on a Stratix III FPGA chip and fully evaluated its performance. Code density tests show that the obtained resolution results lie in the range of (23 ps ~ 37 ps), the differential nonlinearity (DNL) results lie in the range of (-0.4 LSB ~ 0.4 LSB) and the integral nonlinearity (INL) results lie in the range of (-0.7 LSB ~ 0.7 LSB) for each of the 32 TDC channels. This paper greatly eases the designing difficulty of the carry chain RO-based TDCs and can significantly propel their development in practical use.

A 1.6 ps 7 b time to digital converter in 0.18 µm CMOS technology

A fine Time to Digital Converter (TDC) based on time difference amplification is proposed. A current difference based method is introduced to improve the limited input linear range of the conventional×2 Time Amplifier (TA). The modified TA is used in a proposed pipeline TDC to achieve a fine sub-gate delay resolution. A sign detection stage is implemented at the input of the TDC to avoid two separate circuits for conversion of positive and negative inputs, which decreases power consumption by roughly fifty percent. Furthermore, the delay cell circuits are modified to increase the TDC resolution and reduce its susceptibility to mismatch and process variations. The TDC resolution is 1.6ps by post-layout simulation in 180nm CMOS technology. Power consumption of the introduced TDC at 50Msps and 1.2V supply voltage is 280uW.

Increasing a Resolution of Time to Digital Converter

Time to digital converter (TDC) is one of the main blocks of all-digital frequency synthesizer (FS), where it is used as phase detector. The output of TDC is digital, therefore it introduces quantization noise to the output of FS. The resolution of TDC has to be increased, to improve phase noise level at the output of FS. It can be achieved by improving CMOS technology or structure of the TDC. The simplest TDC is based on inverter delay line. Its resolution is inversely proportional to the time interval, which can be measured with such TDC, i.e. delay time of the inverter. Decreasing of this delay is essence of technological increasing of TDC’s resolution. In this work the dependency of inverter delay on technological parameters is shown and its value is calculated in 65 nm CMOS technology. Calculations show, that in this technology delay time of the inverter can vary from 7 ps to 54 ps. If the design is restricted to the usage of specific CMOS technology, in which inverter’s delay does not ensure needed noise level at the output of FS, structure of the TDC needs to be improved. The aim of this improvement is to measure time interval smaller than inverter’s delay. Some of the TDC structures, which can measure sub-inverter delay time, are reviewed in this work: TDC – Vernier delay line, TDC – 2D Vernier plane, stochastic, ring and multistage TDCs.

Cost-Effective Time-to-Digital Converter Using Time-Residue Feedback

This paper proposes a time-residue feedback scheme to balance resolution and complexity in a cell-based time-to-digital converter (TDC). The time residue is amplified and fed back into a cyclic-ring Vernier recursively until it cannot be detected correctly. Only one variable-resolution cyclic-ring Vernier and one tunable delay-chain time amplifier (TA) are adopted. Both coarse and fine oscillators of the proposed Vernier which are designed by the same variable-resolution digital controlled oscillator can be switched off to decrease ground bounce during TA activities. With various control codes, the TDC resolution is also programmable. The test application-specified integrated circuit which has a 13-b resolution and occupies 0.02 mm2 in TSMC 65-nm CMOS process can operate in either feedback or feedforward mode. In feedback mode, the measurements of sampling rate, resolution, input range, differential nonlinearity, and integral nonlinearity are 10 MHz, 0.98 ps, 5.76 ns, ± 0.8 LSB, and ± 2.2 LSB, respectively; it also consumes 3 mW at 1 V supply voltage. The sampling rate, resolution, and power dissipation of the feedforward operation are 250 MHz, 6.01 ps, and 17.5 mW, respectively.

A 0.65--1.35 GHz synthesizable all-digital phase locked loop with quantization noise suppressing time-to-digital converter

This paper presents a new quantization noise suppression method for a time-to-digital converter (TDC) and proposes an all-digital phase-locked loop (ADPLL) architecture using only standard cell logic gates. Using a new multiple input multiple output (MIMO) quantization noise suppression method provides an order of $\sqrt {2N} $ improvement in TDC resolution with $N$ parallel TDC channels. Suppressed noise in the TDC allows the ADPLL to achieve superior jitter performance in both theoretical calculations and simulation results. In order to allow fast portability between process nodes, short design cycle time, ease of modification, and flexibility, ADPLL architecture is designed completely in register transfer level intensive Verilog code and the implementation is synthesized in order to obtain final microelectronic design schematics. In comparison to similar work in the literature, postlayout simulation results show that the designed ADPLL achieves period jitter of 1.78 ps$_{rms}$ with a layout area of 0.09 mm$^{2}$ in 65 nm CMOS process and power consumption of 17.5 mW at 800 MHz.

A 2.2-ps Two-Dimensional Gated-Vernier Time-to-Digital Converter With Digital Calibration

This brief presents a two-dimensional (2-D) Vernier time-to-digital converter (TDC) which uses two 3-stage gated ring oscillators (GROs) in the $X/Y$ Vernier branches. The already small Vernier quantization noise (∼10.6 ps) is improved by the first-order noise shaping of the GRO. Moreover, since all the delay differences between the $X$ and $Y$ phases can be used (rather than only the diagonal line of the one-dimensional architecture), the intrinsic large latency time of the Vernier architecture is dramatically reduced. The TDC is implemented in a 65-nm CMOS process and consumes 2.3 mA from 1.0 V. The measured total noise integrated over a bandwidth of 1.25 MHz yields an equivalent TDC resolution of 2.2 ps, whereas the average latency time (within 2 ns) is less than 1/6 of that in a standard Vernier TDC.

A 4.2 ps Time-Interval RMS Resolution Time-to-Digital Converter Using a Bin Decimation Method in an UltraScale FPGA

The common solution for a field programmable gate array (FPGA)-based time-to-digital converter (TDC) is constructing a tapped delay line (TDL) for time interpolation to yield a sub-clock time resolution. The granularity and uniformity of the delay elements of TDL determine the TDC time resolution. In this paper, we propose a dual-sampling TDL architecture and a bin decimation method that could make the delay elements as small and uniform as possible, so that the implemented TDCs can achieve a high time resolution beyond the intrinsic cell delay. Two identical full hardware-based TDCs were implemented in a Xilinx UltraScale FPGA for performance evaluation. For fixed time intervals in the range from 0 to 440 ns, the average time-interval RMS resolution is measured by the two TDCs with 4.2 ps, thus the timestamp resolution of single TDC is derived as 2.97 ps. The maximum hit rate of the TDC is as high as half the system clock rate of FPGA, namely 250 MHz in our demo prototype. Because the conventional online bin-by-bin calibration is not needed, the implementation of the proposed TDC is straightforward and relatively resource-saving.

A Fractional-N Counter-Assisted DPLL With Parallel Sampling ILFD

A fractional-N digital phase-locked loop (DPLL) with ring oscillator based injection-locked frequency divider (ILFD) and parallel sampling phase samplers is presented. The ILFD utilizes dual path injection technique to achieve wide locking range (4.2–23 GHz) and low power consumption. A low-power parallel sampling phase sampler based time-to-digital converter (TDC), which achieves sub-gate-delay resolution by sampling the ILFD’s multi-phase outputs using parallel sampling technique, is proposed. The TDC resolution is determined by delay spacing between successive sampling clocks, which is ensured through digital calibration loops. Due to injection locking, no calibration is required to normalize the TDC step to the DCO output period. A hybrid high speed counter architecture, combining a 2 bit asynchronous counter and a 6 bit synchronous counter, is proposed to achieve high speed (>4 GHz) operation with low power consumption. The proposed design is fabricated in a 65 nm CMOS process and occupies 0.1 mm2. The synthesizer covers 13.6–16.8 GHz output and dissipates 8.5 mW. The measured output phase noise achieves −89 dBc/Hz and −125 dBc/Hz at 100 kHz and 10 MHz offsets, respectively. The measured jitter is less than 0.43 ps.

High-Fill-Factor &lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$60\times 1$ &lt;/tex-math&gt;&lt;/inline-formula&gt; SPAD Array With 60 Subnanosecond Integrated TDCs

This letter presents a high-fill-factor $60\,\, \times \,\, 1$ linear array of single-photon avalanche diodes (SPADs) and 60 integrated time-to-digital converters (TDCs). The 100- $\mu \text{m}$ diameter SPAD has high photon detection efficiency (50% at 420 nm), very low dark count rate (2.5 kcps at room temperature), and negligible crosstalk ( $\sim 0.1$ % between adjacent pixels). The TDC resolution is 250 ps and its single-shot precision of 200-ps rms is limited just by the quantization noise. Very good linearity ( ${\rm DNL}=5{\%}$ LSB rms and ${\rm INL}=30{\%}$ LSB rms ) is achieved because of the sliding scale technique. The overall fill-factor of the array is 52%. This chip is suitable for many advanced spectroscopic applications, since it provides 60 independent single-photon detectors and the corresponding counting and timing electronics within just one integrated circuit.

Design and performance of a custom ASIC digitizer for wire chamber readout in 65 nm CMOS technology

We present the design and performance of a prototype ASIC digitizer for integrated wire chamber readout, implemented in 65 nm commercial CMOS technology. Each channel of the 4-channel prototype is composed of two 16-bit Time-to-Digital Converters (TDCs), one 8-bit Analog-to-Digital Converter (ADC), a front-end preamplifier and shaper, plus digital and analog buffers that support a variety of digitization chains. The prototype has a multiplexed digital backend that executes a state machine, distributes control and timing signals, and buffers data for serial output. Laboratory bench tests measure the absolute TDC resolution between 74 ps and 480 ps, growing with the absolute delay, and a relative time resolution of 19 ps. Resolution outliers due to cross-talk between clock signals and supply or reference voltages are seen. After calibration, the ADC displays good linearity and noise performance, with an effective number of bits of 6.9. Under normal operating conditions the circuit consumes 32 mW per channel. Potential design improvements to address the resolution drift and tails are discussed.