Implementation of 5.3 ps RMS precision and 350 M samples/second throughput time-to-digital converters with event sampling architecture in a Kintex-7 FPGA

Abstract

Unlike the conventional field programmable gate array (FPGA) based time-to-digital converter (TDC) with clock sampling architecture, the TDC with event sampling architecture implemented in this paper propagates the system clock signal along the tapped-delay line (TDL) and the TDL status is sampled by a hit signal for time interpolation. Since there are several “1–0” and “0–1” transitions in the sampled TDL status, the TDC naturally realizes multiple measurements in parallel without increasing the resource consumption and the measurement dead time. Using a Xilinx Kintex-7 FPGA, we increase the number of equivalent TDC bins approximately to twice the number of physical delay cells in the TDL, which means the TDC resolution is about twice as good as the original. The average RMS precision is measured as 5.3 ps with two identical TDC channels measuring the time intervals in the range 0 to 20 ns. The proposed encoding scheme is so efficient that the TDC measurement throughput can reach 350 M samples per second. The test results show that the event sampling architecture is effective in FPGA as well. The performance that can be achieved is comparable with the performance of their counterparts that use the clock sampling architecture.