Abstract
In a field-programmable gate array (FPGA)-based time-to-digital converter (TDC), the hit signal to be measured launches out a segment of the clock-like signal propagating along the tapped delay line (TDL). If every edge of the clock-like signal in the TDL status is identified by the encoder, parallel multiple measurements can be achieved to improve the TDC time precision. In this article, we propose a bubble-proof multi-edge encoding scheme by hardware in pipeline fashion, which can achieve 277-MSamples/s measurement throughput on a Kintex-7 FPGA. Based on the encoding scheme, TDCs with 1-, 2-, 4-, 6-, and 8-edge multiple measurements are sequentially implemented. The corresponding average rms precisions measuring time intervals from 0 to 50 ns are evaluated as 8.2, 4.8, 3.5, 3.1, and 3.0 ps, respectively. The test results confirm that the proposed TDC with a multi-edge encoding scheme can effectively improve TDC time precision without adding TDC measurement dead time. Its resource-saving feature also makes it feasible for multi-channel TDC integration.
Published Version
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call