Abstract
Taking the system clock as the reference, a ring-oscillator based Vernier-type time stamping method is proposed for the implementation of time-to-digital converters (TDCs) on field programmable gate array (FPGA). A module with this method called time-marker is implemented on a Xilinx Kintex-7 FPGA and tested with 43 ps time resolution and less than 50 ns measurement dead time. To illustrate this time-marker can be used as the building block for TDC construction to provide high time measurement performance with low resource consumption, a multi-mode TDC using eight time-markers is implemented with performance evaluation. The TDC has three flexible configuration modes for performance enhancements in three aspects. In the multi-channel mode, it becomes eight independent TDC channels with average 34 ps time interval RMS precision and 50 ns measurement dead time; in the high-precision mode, it is one TDC channel with 14 ps RMS precision and 50 ns measurement dead time; and in the high-throughput mode, it is one TDC channel with 33 ps RMS precision and 6.25 ns measurement dead time. In addition, the temperature dependence of the performance is evaluated.
Published Version
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